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| author | QingShan Zhang <qshanz@cn.ibm.com> | 2018-08-20 02:52:55 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2018-08-20 02:52:55 +0000 |
| commit | f8f9af7ba529ab900eba783fa76229f77a545e07 (patch) | |
| tree | d213eade4c2f88037e22c55847afd8e1b689b128 /llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll | |
| parent | fdca0c6d2ea9b2d30965f8f170d705a858c43b9d (diff) | |
| download | bcm5719-llvm-f8f9af7ba529ab900eba783fa76229f77a545e07.tar.gz bcm5719-llvm-f8f9af7ba529ab900eba783fa76229f77a545e07.zip | |
[PowerPC] Add a peephole post RA to transform the inst that fed by add
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e.
y = add imm, reg
LFDX. 0, y
-->
LFD imm(reg)
Reviewers: Nemanjai
Differential Revision: https://reviews.llvm.org/D49007
llvm-svn: 340149
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll b/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll index 8a95de3a0cb..e3d528241e0 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64VSX +; RUN: llc < %s -O0 -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=false | FileCheck %s --check-prefix=ELF64VSX ;; The semantics of VSX stores for when R0 is used is different depending on ;; whether it is used as base or offset. If used as base, the effective |
