summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
diff options
context:
space:
mode:
authorJustin Hibbits <jrh29@alumni.cwru.edu>2018-07-18 04:25:10 +0000
committerJustin Hibbits <jrh29@alumni.cwru.edu>2018-07-18 04:25:10 +0000
commitd52990c71b6f83c9beeba4efc9103412e0416ba9 (patch)
treefebc0bdc8253b60c767bc182970d894684843e06 /llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
parent4fa4fa6a73a7829494df8272ef49825fb2066d1a (diff)
downloadbcm5719-llvm-d52990c71b6f83c9beeba4efc9103412e0416ba9.tar.gz
bcm5719-llvm-d52990c71b6f83c9beeba4efc9103412e0416ba9.zip
Introduce codegen for the Signal Processing Engine
Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 llvm-svn: 337347
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll')
-rw-r--r--llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
index 5881dc3798a..004b82f09b8 100644
--- a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
@@ -3,13 +3,16 @@
; When fastisel better supports VSX fix up this test case.
;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
define void @t1a(float %a) nounwind {
entry:
; ELF64: t1a
+; SPE: t1a
%cmp = fcmp oeq float %a, 0.000000e+00
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
+; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -25,10 +28,12 @@ declare void @foo()
define void @t1b(float %a) nounwind {
entry:
; ELF64: t1b
+; SPE: t1b
%cmp = fcmp oeq float %a, -0.000000e+00
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
+; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -42,10 +47,12 @@ if.end: ; preds = %if.then, %entry
define void @t2a(double %a) nounwind {
entry:
; ELF64: t2a
+; SPE: t2a
%cmp = fcmp oeq double %a, 0.000000e+00
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
+; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -59,10 +66,12 @@ if.end: ; preds = %if.then, %entry
define void @t2b(double %a) nounwind {
entry:
; ELF64: t2b
+; SPE: t2b
%cmp = fcmp oeq double %a, -0.000000e+00
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
+; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
OpenPOWER on IntegriCloud