diff options
| author | Juergen Ributzka <juergen@apple.com> | 2014-08-13 22:08:02 +0000 |
|---|---|---|
| committer | Juergen Ributzka <juergen@apple.com> | 2014-08-13 22:08:02 +0000 |
| commit | 7cee768e55ca9fd67859e0794e3906e0eb5a0623 (patch) | |
| tree | 3074aece39a1ad87df88ccf56741c0495a0116bc /llvm/test/CodeGen/PowerPC/fast-isel-call.ll | |
| parent | fe2c11ffd6b0ac7686ac99ad5e53e6a8e3dfe151 (diff) | |
| download | bcm5719-llvm-7cee768e55ca9fd67859e0794e3906e0eb5a0623.tar.gz bcm5719-llvm-7cee768e55ca9fd67859e0794e3906e0eb5a0623.zip | |
[FastISel] Let the target decide first if it wants to materialize a constant.
This changes the order in which FastISel tries to materialize a constant.
Originally it would try to use a simple target-independent approach, which
can lead to the generation of inefficient code.
On X86 this would result in the use of movabsq to materialize any 64bit
integer constant - even for simple and small values such as 0 and 1. Also
some very funny floating-point materialization could be observed too.
On AArch64 it would materialize the constant 0 in a register even the
architecture has an actual "zero" register.
On ARM it would generate unnecessary mov instructions or not use mvn.
This change simply changes the order and always asks the target first if it
likes to materialize the constant. This doesn't fix all the issues
mentioned above, but it enables the targets to implement such
optimizations.
Related to <rdar://problem/17420988>.
llvm-svn: 215588
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/fast-isel-call.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-call.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll index 33a8ba903e3..223090523c4 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll @@ -57,11 +57,11 @@ entry: ; ELF64: t10 %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70) ; ELF64: li 3, 0 -; ELF64: li 4, 248 -; ELF64: li 5, 187 +; ELF64: li 4, -8 +; ELF64: li 5, -69 ; ELF64: li 6, 28 ; ELF64: li 7, 40 -; ELF64: li 8, 186 +; ELF64: li 8, -70 ; ELF64: rldicl 3, 3, 0, 56 ; ELF64: rldicl 4, 4, 0, 56 ; ELF64: rldicl 5, 5, 0, 56 |
