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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-07-25 18:26:35 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-07-25 18:26:35 +0000 |
| commit | 009016bb702f7012850d068053f6ca553f2180b5 (patch) | |
| tree | 28226774baab54a2138225fd9dfbc9b28f85a4b2 /llvm/test/CodeGen/PowerPC/expand-isel.ll | |
| parent | d74d890247ecb3a0e41e99f58be32eeb182ab659 (diff) | |
| download | bcm5719-llvm-009016bb702f7012850d068053f6ca553f2180b5.tar.gz bcm5719-llvm-009016bb702f7012850d068053f6ca553f2180b5.zip | |
[PowerPC] Pretty-print CR bits the way the binutils disassembler does
This patch just adds printing of CR bit registers in a more human-readable
form akin to that used by the GNU binutils.
Differential Revision: https://reviews.llvm.org/D31494
llvm-svn: 309001
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/expand-isel.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/expand-isel.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll index c8707bda8e8..608f0367cbc 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel.ll +++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll @@ -12,7 +12,7 @@ entry: ; CHECK-LABEL: @testExpandISELToIfElse ; CHECK: addi r5, r3, 1 ; CHECK-NEXT: cmpwi cr0, r3, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] @@ -32,7 +32,7 @@ entry: ; CHECK-LABEL: @testExpandISELToIf ; CHECK: cmpwi r3, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: blr ; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: addi r3, r4, 0 @@ -48,7 +48,7 @@ entry: ; CHECK-LABEL: @testExpandISELToElse ; CHECK: cmpwi r3, 0 -; CHECK-NEXT: bclr 12, 1, 0 +; CHECK-NEXT: bclr 12, gt, 0 ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: blr } @@ -95,7 +95,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs ; CHECK: cmpwi r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: ori r12, r6, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] @@ -121,7 +121,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI ; CHECK: cmpwi cr0, r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: ori r12, r6, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] @@ -148,7 +148,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI ; CHECK: cmpwi cr0, r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r5, r6, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] @@ -176,7 +176,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs ; CHECK: cmpwi cr0, r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: addi r4, r3, 0 |
