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authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>2015-04-09 23:54:37 +0000
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>2015-04-09 23:54:37 +0000
commitc09047916a139ebc07f789bae4c213753906e341 (patch)
treed73938ee7c21f3c8a9a174213da254f90d4c2fba /llvm/test/CodeGen/PowerPC/div-e-all.ll
parent696c88753fe7db17f98b4fd6495bd71702675648 (diff)
downloadbcm5719-llvm-c09047916a139ebc07f789bae4c213753906e341.tar.gz
bcm5719-llvm-c09047916a139ebc07f789bae4c213753906e341.zip
Add LLVM support for remaining integer divide and permute instructions from ISA 2.06
This is the patch corresponding to review: http://reviews.llvm.org/D8406 It adds some missing instructions from ISA 2.06 to the PPC back end. llvm-svn: 234546
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/div-e-all.ll')
-rw-r--r--llvm/test/CodeGen/PowerPC/div-e-all.ll54
1 files changed, 54 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/div-e-all.ll b/llvm/test/CodeGen/PowerPC/div-e-all.ll
new file mode 100644
index 00000000000..912deeb2b3e
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/div-e-all.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define signext i32 @test1() #0 {
+entry:
+ %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
+ ret i32 %0
+; CHECK: divwe 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divwe(i32, i32) #1
+
+; Function Attrs: nounwind
+define signext i32 @test2() #0 {
+entry:
+ %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16)
+ ret i32 %0
+; CHECK: divweu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divweu(i32, i32) #1
+
+; Function Attrs: nounwind
+define i64 @test3() #0 {
+entry:
+ %0 = call i64 @llvm.ppc.divde(i64 32, i64 16)
+ ret i64 %0
+; CHECK: divde 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.divde(i64, i64) #1
+
+; Function Attrs: nounwind
+define i64 @test4() #0 {
+entry:
+ %0 = call i64 @llvm.ppc.divdeu(i64 32, i64 16)
+ ret i64 %0
+; CHECK: divdeu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.divdeu(i64, i64) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"}
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