diff options
| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-05-02 01:47:34 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-05-02 01:47:34 +0000 |
| commit | b89c27f5150e104b8aed1b866456e2e4dc2296a3 (patch) | |
| tree | eeebf6567b391a6c0cc78c8ae0111429f84c1237 /llvm/test/CodeGen/PowerPC/build-vector-tests.ll | |
| parent | c190f96b7dbd1c3462a3cf7bd5faa6fb9866424d (diff) | |
| download | bcm5719-llvm-b89c27f5150e104b8aed1b866456e2e4dc2296a3.tar.gz bcm5719-llvm-b89c27f5150e104b8aed1b866456e2e4dc2296a3.zip | |
[PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE
Fixes PR30730.
This is a re-commit of a pulled commit. The commit was pulled because some
software projects contained uses of Altivec vectors that violated alignment
requirements. Known issues have now been fixed.
Committing on behalf of Lei Huang.
Differential Revision: https://reviews.llvm.org/D26861
llvm-svn: 301892
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/build-vector-tests.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/build-vector-tests.ll | 46 |
1 files changed, 20 insertions, 26 deletions
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll index fa4d212932f..1bce9d4cb43 100644 --- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll @@ -875,8 +875,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -942,8 +942,7 @@ entry: ; P8BE: vperm ; P8BE: blr ; P8LE: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx ; P8LE: xxswapd ; P8LE: vperm ; P8LE: blr @@ -1036,7 +1035,6 @@ entry: ; P8LE: sldi {{r[0-9]+}}, r4, 2 ; P8LE-DAG: lxvd2x ; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd ; P8LE: xxswapd ; P8LE: vperm ; P8LE: blr @@ -1289,8 +1287,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -1315,7 +1313,7 @@ entry: ; P8BE: xvcvspsxws v2, [[REG1]] ; P8BE: blr ; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 -; P8LE: xxswapd v2, [[REG1]] +; P8LE: xxswapd ; P8LE: xvcvspsxws v2, v2 ; P8LE: blr } @@ -1359,8 +1357,7 @@ entry: ; P8BE: xvcvspsxws ; P8BE: blr ; P8LE: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx ; P8LE: xxswapd ; P8LE: vperm ; P8LE: xvcvspsxws @@ -1566,8 +1563,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -2036,8 +2033,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -2103,8 +2100,8 @@ entry: ; P8BE: vperm ; P8BE: blr ; P8LE: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx +; P8LE-NOT: xxswapd ; P8LE: xxswapd ; P8LE: vperm ; P8LE: blr @@ -2195,10 +2192,8 @@ entry: ; P8BE: vperm ; P8BE: blr ; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2 -; P8LE-DAG: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd -; P8LE: xxswapd +; P8LE-DAG: lvx +; P8LE-DAG: lvx ; P8LE: vperm ; P8LE: blr } @@ -2450,8 +2445,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -2519,9 +2514,8 @@ entry: ; P8BE: vperm ; P8BE: xvcvspuxws ; P8BE: blr -; P8LE: lxvd2x ; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx ; P8LE: xxswapd ; P8LE: vperm ; P8LE: xvcvspuxws @@ -2727,8 +2721,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } |
