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author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2018-10-12 14:02:20 +0000 |
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committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2018-10-12 14:02:20 +0000 |
commit | 9552dd187aadd92aeacda13ad4294be12ebe85ab (patch) | |
tree | 9a86aed6ec0c14911d055cd10d6164019beea7f0 /llvm/test/CodeGen/PowerPC/bitfieldinsert.ll | |
parent | 6cbb3ca456e3bf0405c54b5a593c86673606a5ea (diff) | |
download | bcm5719-llvm-9552dd187aadd92aeacda13ad4294be12ebe85ab.tar.gz bcm5719-llvm-9552dd187aadd92aeacda13ad4294be12ebe85ab.zip |
[PowerPC] avoid masking already-zero bits in BitPermutationSelector
The current BitPermutationSelector generates a code to build a value by tracking two types of bits: ConstZero and Variable.
ConstZero means a bit we need to mask off and Variable is a bit we copy from an input value.
This patch add third type of bits VariableKnownToBeZero caused by AssertZext node or zero-extending load node.
VariableKnownToBeZero means a bit comes from an input value, but it is known to be already zero. So we do not need to mask them.
VariableKnownToBeZero enhances flexibility to group bits, since we can avoid redundant masking for these bits.
This patch also renames "HasZero" to "NeedMask" since now we may skip masking even when we have zeros (of type VariableKnownToBeZero).
Differential Revision: https://reviews.llvm.org/D48025
llvm-svn: 344347
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/bitfieldinsert.ll')
-rw-r--r-- | llvm/test/CodeGen/PowerPC/bitfieldinsert.ll | 35 |
1 files changed, 32 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll b/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll index e654c7d8a0c..76a648b6f13 100644 --- a/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll +++ b/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll @@ -1,6 +1,35 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; equivalent C code +; struct s64 { +; int a:5; +; int b:16; +; long c:42; +; }; +; void bitfieldinsert64(struct s *p, unsigned short v) { +; p->b = v; +; } + +%struct.s64 = type { i64 } + +define void @bitfieldinsert64(%struct.s64* nocapture %p, i16 zeroext %v) { +; CHECK-LABEL: @bitfieldinsert64 +; CHECK: ld [[REG1:[0-9]+]], 0(3) +; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26 +; CHECK-NEXT: std [[REG1]], 0(3) +; CHECK-NEXT: blr +entry: + %0 = getelementptr inbounds %struct.s64, %struct.s64* %p, i64 0, i32 0 + %1 = zext i16 %v to i64 + %bf.load = load i64, i64* %0, align 8 + %bf.shl = shl nuw nsw i64 %1, 5 + %bf.clear = and i64 %bf.load, -2097121 + %bf.set = or i64 %bf.clear, %bf.shl + store i64 %bf.set, i64* %0, align 8 + ret void +} + ; bitfieldinsert32: Test for rlwimi ; equivalent C code ; struct s32 { @@ -17,9 +46,9 @@ define void @bitfieldinsert32(%struct.s32* nocapture %p, i32 zeroext %v) { ; CHECK-LABEL: @bitfieldinsert32 ; CHECK: lwz [[REG1:[0-9]+]], 0(3) -; CHECK: rlwimi [[REG1]], 4, 8, 8, 23 -; CHECK: stw [[REG1]], 0(3) -; CHECK: blr +; CHECK-NEXT: rlwimi [[REG1]], 4, 8, 8, 23 +; CHECK-NEXT: stw [[REG1]], 0(3) +; CHECK-NEXT: blr entry: %0 = getelementptr inbounds %struct.s32, %struct.s32* %p, i64 0, i32 0 %bf.load = load i32, i32* %0, align 4 |