[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX

The match pattern in the definition of LXSDX is xoaddr, so the Pseudo
instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post
RA based on the register pressure. To avoid ambiguity, we need to remove the
select pattern for LXSDX, same as what was done for LXSD. STXSDX also have
the same issue.

Patch by Qing Shan Zhang (steven.zhang).

Differential Revision: https://reviews.llvm.org/D47178

llvm-svn: 333150

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll b/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
index d6c7dd3804f..e5fd9f50a06 100644
--- a/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
+++ b/llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
@@ -18,7 +18,7 @@ define i64 @f64toi64(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
-; CHECK-P7: stxsdx 1,
+; CHECK-P7: stfdx 1,
 ; CHECK-P7: ld 3,
 ; CHECK: mffprd 3, 1
 }
@@ -39,7 +39,7 @@ entry:
   %0 = bitcast i64 %a to double
   ret double %0
 ; CHECK-P7: std 3,
-; CHECK-P7: lxsdx 1,
+; CHECK-P7: lfdx 1,
 ; CHECK: mtvsrd 1, 3
 }
 
@@ -58,7 +58,7 @@ define i64 @f64toi64u(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
-; CHECK-P7: stxsdx 1,
+; CHECK-P7: stfdx 1,
 ; CHECK-P7: ld 3,
 ; CHECK: mffprd 3, 1
 }
@@ -79,6 +79,6 @@ entry:
   %0 = bitcast i64 %a to double
   ret double %0
 ; CHECK-P7: std 3,
-; CHECK-P7: lxsdx 1,
+; CHECK-P7: lfdx 1,
 ; CHECK: mtvsrd 1, 3
 }