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| author | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 18:51:49 +0000 |
|---|---|---|
| committer | Justin Holewinski <jholewinski@nvidia.com> | 2013-06-21 18:51:49 +0000 |
| commit | b6e6cd356e3be97e4412cddeeaa71269a5919fca (patch) | |
| tree | fab6245c42fd56f368d5ee5429440408e9c22e3f /llvm/test/CodeGen/NVPTX | |
| parent | 7ceab3a892b763aa8dae2c998ab7fad4badfafc9 (diff) | |
| download | bcm5719-llvm-b6e6cd356e3be97e4412cddeeaa71269a5919fca.tar.gz bcm5719-llvm-b6e6cd356e3be97e4412cddeeaa71269a5919fca.zip | |
[NVPTX] Add support for selecting CUDA vs OCL mode based on triple
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl"
llvm-svn: 184579
Diffstat (limited to 'llvm/test/CodeGen/NVPTX')
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/i1-global.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/i1-param.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/load-sext-i1.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/refl1.ll | 4 |
5 files changed, 11 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll b/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll index c9cb2f71f42..2a527989e41 100644 --- a/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll +++ b/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" +target triple = "nvptx-nvidia-cuda" ; Ensure global variables in address space 0 are promoted to address space 1 diff --git a/llvm/test/CodeGen/NVPTX/i1-global.ll b/llvm/test/CodeGen/NVPTX/i1-global.ll index 0595325977e..1dd8ae40db4 100644 --- a/llvm/test/CodeGen/NVPTX/i1-global.ll +++ b/llvm/test/CodeGen/NVPTX/i1-global.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" - +target triple = "nvptx-nvidia-cuda" ; CHECK: .visible .global .align 1 .u8 mypred @mypred = addrspace(1) global i1 true, align 1 diff --git a/llvm/test/CodeGen/NVPTX/i1-param.ll b/llvm/test/CodeGen/NVPTX/i1-param.ll index fabd61a25d2..f4df8743932 100644 --- a/llvm/test/CodeGen/NVPTX/i1-param.ll +++ b/llvm/test/CodeGen/NVPTX/i1-param.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" +target triple = "nvptx-nvidia-cuda" ; Make sure predicate (i1) operands to kernels get expanded out to .u8 diff --git a/llvm/test/CodeGen/NVPTX/load-sext-i1.ll b/llvm/test/CodeGen/NVPTX/load-sext-i1.ll index c9b2e9793bb..d836740eed9 100644 --- a/llvm/test/CodeGen/NVPTX/load-sext-i1.ll +++ b/llvm/test/CodeGen/NVPTX/load-sext-i1.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" - +target triple = "nvptx-nvidia-cuda" define void @main(i1* %a1, i32 %a2, i32* %arg3) { ; CHECK: ld.u8 diff --git a/llvm/test/CodeGen/NVPTX/refl1.ll b/llvm/test/CodeGen/NVPTX/refl1.ll index 5a9dac152e4..4aeff092495 100644 --- a/llvm/test/CodeGen/NVPTX/refl1.ll +++ b/llvm/test/CodeGen/NVPTX/refl1.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +target triple = "nvptx-nvidia-cuda" ; Function Attrs: nounwind ; CHECK: .entry foo |
