[MIPS GlobalISel] Register bank select for G_STORE. Select i64 store

Select gprb or fprb when stored value is defined by either:
 copy from physical register or
 instruction with only one mapping available for that def operand.

Store of integer s64 is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.

Differential Revision: https://reviews.llvm.org/D64268

llvm-svn: 365322

3 files changed, 225 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
new file mode 100644
index 00000000000..ab4c83b286e
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
@@ -0,0 +1,98 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @store_i32(i32* %ptr) { entry: ret void }
+  define void @store_i64(i64* %ptr) { entry: ret void }
+  define void @store_float(float* %ptr) { entry: ret void }
+  define void @store_double(double* %ptr) { entry: ret void }
+
+...
+---
+name:            store_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: store_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.ptr)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(p0) = COPY $a1
+    G_STORE %0(s32), %1(p0) :: (store 4 into %ir.ptr)
+    RetRA
+
+...
+---
+name:            store_i64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: store_i64
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+    ; MIPS32: G_STORE [[MV]](s64), [[COPY2]](p0) :: (store 8 into %ir.ptr)
+    ; MIPS32: RetRA
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %1:_(p0) = COPY $a2
+    G_STORE %0(s64), %1(p0) :: (store 8 into %ir.ptr)
+    RetRA
+
+...
+---
+name:            store_float
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $f12
+
+    ; MIPS32-LABEL: name: store_float
+    ; MIPS32: liveins: $a1, $f12
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.ptr)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $f12
+    %1:_(p0) = COPY $a1
+    G_STORE %0(s32), %1(p0) :: (store 4 into %ir.ptr)
+    RetRA
+
+...
+---
+name:            store_double
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $d6
+
+    ; MIPS32-LABEL: name: store_double
+    ; MIPS32: liveins: $a2, $d6
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a2
+    ; MIPS32: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.ptr)
+    ; MIPS32: RetRA
+    %0:_(s64) = COPY $d6
+    %1:_(p0) = COPY $a2
+    G_STORE %0(s64), %1(p0) :: (store 8 into %ir.ptr)
+    RetRA
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store.ll
new file mode 100644
index 00000000000..0bad24c51fe
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define void @store_i32(i32 %val, i32* %ptr)  {
+; MIPS32-LABEL: store_i32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sw $4, 0($5)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  store i32 %val, i32* %ptr
+  ret void
+}
+
+define void @store_i64(i64 %val, i64* %ptr)  {
+; MIPS32-LABEL: store_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sw $4, 0($6)
+; MIPS32-NEXT:    ori $1, $zero, 4
+; MIPS32-NEXT:    addu $1, $6, $1
+; MIPS32-NEXT:    sw $5, 0($1)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  store i64 %val, i64* %ptr
+  ret void
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
new file mode 100644
index 00000000000..03c5a867f4b
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
@@ -0,0 +1,100 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @store_i32(i32* %ptr) { entry: ret void }
+  define void @store_i64(i64* %ptr) { entry: ret void }
+  define void @store_float(float* %ptr) { entry: ret void }
+  define void @store_double(double* %ptr) { entry: ret void }
+
+...
+---
+name:            store_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: store_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.ptr)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(p0) = COPY $a1
+    G_STORE %0(s32), %1(p0) :: (store 4 into %ir.ptr)
+    RetRA
+
+...
+---
+name:            store_i64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32-LABEL: name: store_i64
+    ; MIPS32: liveins: $a0, $a1, $a2
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+    ; MIPS32: G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store 4 into %ir.ptr, align 8)
+    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
+    ; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY2]], [[C]](s32)
+    ; MIPS32: G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.ptr + 4, align 8)
+    ; MIPS32: RetRA
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %1:_(p0) = COPY $a2
+    G_STORE %0(s64), %1(p0) :: (store 8 into %ir.ptr)
+    RetRA
+
+...
+---
+name:            store_float
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $f12
+
+    ; MIPS32-LABEL: name: store_float
+    ; MIPS32: liveins: $a1, $f12
+    ; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.ptr)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $f12
+    %1:_(p0) = COPY $a1
+    G_STORE %0(s32), %1(p0) :: (store 4 into %ir.ptr)
+    RetRA
+
+...
+---
+name:            store_double
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $d6
+
+    ; MIPS32-LABEL: name: store_double
+    ; MIPS32: liveins: $a2, $d6
+    ; MIPS32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a2
+    ; MIPS32: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.ptr)
+    ; MIPS32: RetRA
+    %0:_(s64) = COPY $d6
+    %1:_(p0) = COPY $a2
+    G_STORE %0(s64), %1(p0) :: (store 8 into %ir.ptr)
+    RetRA
+
+...