[MIPS GlobalISel] Lower uitofp

Add custom lowering for G_UITOFP for MIPS32.

Differential Revision: https://reviews.llvm.org/D66930

llvm-svn: 370432

2 files changed, 445 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
index 7a8ed1e3a6a..100a88b89df 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
@@ -12,7 +12,13 @@
   define void @i16tof64() {entry: ret void}
   define void @i8tof64() {entry: ret void}
   define void @u64tof32() {entry: ret void}
+  define void @u32tof32() {entry: ret void}
+  define void @u16tof32() {entry: ret void}
+  define void @u8tof32() {entry: ret void}
   define void @u64tof64() {entry: ret void}
+  define void @u32tof64() {entry: ret void}
+  define void @u16tof64() {entry: ret void}
+  define void @u8tof64() {entry: ret void}
 
 ...
 ---
@@ -328,6 +334,124 @@ body:             |
 
 ...
 ---
+name:            u32tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: u32tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
+    ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
+    ; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
+    ; FP32: $f0 = COPY [[FPTRUNC]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: u32tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
+    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
+    ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
+    ; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
+    ; FP64: $f0 = COPY [[FPTRUNC]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_UITOFP %0(s32)
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            u16tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: u16tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
+    ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
+    ; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
+    ; FP32: $f0 = COPY [[FPTRUNC]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: u16tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
+    ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
+    ; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
+    ; FP64: $f0 = COPY [[FPTRUNC]](s32)
+    ; FP64: RetRA implicit $f0
+    %1:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %1(s32)
+    %2:_(s32) = G_UITOFP %0(s16)
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            u8tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: u8tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
+    ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
+    ; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
+    ; FP32: $f0 = COPY [[FPTRUNC]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: u8tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
+    ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
+    ; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
+    ; FP64: $f0 = COPY [[FPTRUNC]](s32)
+    ; FP64: RetRA implicit $f0
+    %1:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %1(s32)
+    %2:_(s32) = G_UITOFP %0(s8)
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
 name:            u64tof64
 alignment:       2
 tracksRegLiveness: true
@@ -367,3 +491,115 @@ body:             |
     RetRA implicit $d0
 
 ...
+---
+name:            u32tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: u32tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
+    ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
+    ; FP32: $d0 = COPY [[FSUB]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: u32tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
+    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
+    ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
+    ; FP64: $d0 = COPY [[FSUB]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s32) = COPY $a0
+    %1:_(s64) = G_UITOFP %0(s32)
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            u16tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: u16tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
+    ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
+    ; FP32: $d0 = COPY [[FSUB]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: u16tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
+    ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
+    ; FP64: $d0 = COPY [[FSUB]](s64)
+    ; FP64: RetRA implicit $d0
+    %1:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %1(s32)
+    %2:_(s64) = G_UITOFP %0(s16)
+    $d0 = COPY %2(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            u8tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: u8tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
+    ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
+    ; FP32: $d0 = COPY [[FSUB]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: u8tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
+    ; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
+    ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
+    ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
+    ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
+    ; FP64: $d0 = COPY [[FSUB]](s64)
+    ; FP64: RetRA implicit $d0
+    %1:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %1(s32)
+    %2:_(s64) = G_UITOFP %0(s8)
+    $d0 = COPY %2(s64)
+    RetRA implicit $d0
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
index 3803c661e17..6406f64d82b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
@@ -136,6 +136,114 @@ entry:
   ret float %conv
 }
 
+
+define float @u32tof32(i32 zeroext %a) {
+; FP32-LABEL: u32tof32:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    mtc1 $4, $f0
+; FP32-NEXT:    mtc1 $1, $f1
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    ori $2, $zero, 0
+; FP32-NEXT:    mtc1 $2, $f2
+; FP32-NEXT:    mtc1 $1, $f3
+; FP32-NEXT:    sub.d $f0, $f0, $f2
+; FP32-NEXT:    cvt.s.d $f0, $f0
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: u32tof32:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    mtc1 $4, $f0
+; FP64-NEXT:    mthc1 $1, $f0
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    ori $2, $zero, 0
+; FP64-NEXT:    mtc1 $2, $f1
+; FP64-NEXT:    mthc1 $1, $f1
+; FP64-NEXT:    sub.d $f0, $f0, $f1
+; FP64-NEXT:    cvt.s.d $f0, $f0
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %conv = uitofp i32 %a to float
+  ret float %conv
+}
+
+define float @u16tof32(i16 zeroext %a) {
+; FP32-LABEL: u16tof32:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    ori $1, $zero, 65535
+; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    lui $2, 17200
+; FP32-NEXT:    mtc1 $1, $f0
+; FP32-NEXT:    mtc1 $2, $f1
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    ori $2, $zero, 0
+; FP32-NEXT:    mtc1 $2, $f2
+; FP32-NEXT:    mtc1 $1, $f3
+; FP32-NEXT:    sub.d $f0, $f0, $f2
+; FP32-NEXT:    cvt.s.d $f0, $f0
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: u16tof32:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    ori $1, $zero, 65535
+; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    lui $2, 17200
+; FP64-NEXT:    mtc1 $1, $f0
+; FP64-NEXT:    mthc1 $2, $f0
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    ori $2, $zero, 0
+; FP64-NEXT:    mtc1 $2, $f1
+; FP64-NEXT:    mthc1 $1, $f1
+; FP64-NEXT:    sub.d $f0, $f0, $f1
+; FP64-NEXT:    cvt.s.d $f0, $f0
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %conv = uitofp i16 %a to float
+  ret float %conv
+}
+
+define float @u8tof32(i8 zeroext %a) {
+; FP32-LABEL: u8tof32:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    ori $1, $zero, 255
+; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    lui $2, 17200
+; FP32-NEXT:    mtc1 $1, $f0
+; FP32-NEXT:    mtc1 $2, $f1
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    ori $2, $zero, 0
+; FP32-NEXT:    mtc1 $2, $f2
+; FP32-NEXT:    mtc1 $1, $f3
+; FP32-NEXT:    sub.d $f0, $f0, $f2
+; FP32-NEXT:    cvt.s.d $f0, $f0
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: u8tof32:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    ori $1, $zero, 255
+; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    lui $2, 17200
+; FP64-NEXT:    mtc1 $1, $f0
+; FP64-NEXT:    mthc1 $2, $f0
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    ori $2, $zero, 0
+; FP64-NEXT:    mtc1 $2, $f1
+; FP64-NEXT:    mthc1 $1, $f1
+; FP64-NEXT:    sub.d $f0, $f0, $f1
+; FP64-NEXT:    cvt.s.d $f0, $f0
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %conv = uitofp i8 %a to float
+  ret float %conv
+}
+
 define double @u64tof64(i64 zeroext %a) {
 ; MIPS32-LABEL: u64tof64:
 ; MIPS32:       # %bb.0: # %entry
@@ -153,3 +261,104 @@ entry:
   %conv = uitofp i64 %a to double
   ret double %conv
 }
+
+define double @u32tof64(i32 zeroext %a) {
+; FP32-LABEL: u32tof64:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    mtc1 $4, $f0
+; FP32-NEXT:    mtc1 $1, $f1
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    ori $2, $zero, 0
+; FP32-NEXT:    mtc1 $2, $f2
+; FP32-NEXT:    mtc1 $1, $f3
+; FP32-NEXT:    sub.d $f0, $f0, $f2
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: u32tof64:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    mtc1 $4, $f0
+; FP64-NEXT:    mthc1 $1, $f0
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    ori $2, $zero, 0
+; FP64-NEXT:    mtc1 $2, $f1
+; FP64-NEXT:    mthc1 $1, $f1
+; FP64-NEXT:    sub.d $f0, $f0, $f1
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %conv = uitofp i32 %a to double
+  ret double %conv
+}
+
+define double @u16tof64(i16 zeroext %a) {
+; FP32-LABEL: u16tof64:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    ori $1, $zero, 65535
+; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    lui $2, 17200
+; FP32-NEXT:    mtc1 $1, $f0
+; FP32-NEXT:    mtc1 $2, $f1
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    ori $2, $zero, 0
+; FP32-NEXT:    mtc1 $2, $f2
+; FP32-NEXT:    mtc1 $1, $f3
+; FP32-NEXT:    sub.d $f0, $f0, $f2
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: u16tof64:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    ori $1, $zero, 65535
+; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    lui $2, 17200
+; FP64-NEXT:    mtc1 $1, $f0
+; FP64-NEXT:    mthc1 $2, $f0
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    ori $2, $zero, 0
+; FP64-NEXT:    mtc1 $2, $f1
+; FP64-NEXT:    mthc1 $1, $f1
+; FP64-NEXT:    sub.d $f0, $f0, $f1
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %conv = uitofp i16 %a to double
+  ret double %conv
+}
+
+define double @u8tof64(i8 zeroext %a) {
+; FP32-LABEL: u8tof64:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    ori $1, $zero, 255
+; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    lui $2, 17200
+; FP32-NEXT:    mtc1 $1, $f0
+; FP32-NEXT:    mtc1 $2, $f1
+; FP32-NEXT:    lui $1, 17200
+; FP32-NEXT:    ori $2, $zero, 0
+; FP32-NEXT:    mtc1 $2, $f2
+; FP32-NEXT:    mtc1 $1, $f3
+; FP32-NEXT:    sub.d $f0, $f0, $f2
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: u8tof64:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    ori $1, $zero, 255
+; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    lui $2, 17200
+; FP64-NEXT:    mtc1 $1, $f0
+; FP64-NEXT:    mthc1 $2, $f0
+; FP64-NEXT:    lui $1, 17200
+; FP64-NEXT:    ori $2, $zero, 0
+; FP64-NEXT:    mtc1 $2, $f1
+; FP64-NEXT:    mthc1 $1, $f1
+; FP64-NEXT:    sub.d $f0, $f0, $f1
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %conv = uitofp i8 %a to double
+  ret double %conv
+}