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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-08-01 15:32:51 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-08-01 15:32:51 +0000 |
| commit | b3ae33c7a60f6df087d5f337eefdfce8c2887f68 (patch) | |
| tree | 2ff4c83e490ed3aeca283d54049b87e621f21f1f /llvm/test/CodeGen/Mips | |
| parent | 728b9abb3f6e5aa67687ddc34a29d547f2d26a0d (diff) | |
| download | bcm5719-llvm-b3ae33c7a60f6df087d5f337eefdfce8c2887f68.tar.gz bcm5719-llvm-b3ae33c7a60f6df087d5f337eefdfce8c2887f68.zip | |
[mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.
Summary:
Allocating an AFGR64 shadows two GPR32's instead of just one.
This fixes an LNT regression detected by our internal buildbots.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D23012
llvm-svn: 277348
Diffstat (limited to 'llvm/test/CodeGen/Mips')
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll index 8f762b0ed08..b3fc58f293a 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll @@ -80,6 +80,20 @@ entry: ret float %res } +define float @sel_float2(float %k, float %l, i32 %j) { +entry: + ; CHECK-LABEL: sel_float2: + + ; CHECK-DAG: xor $[[T0:[0-9]+]], $6, $zero + ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK: movn.s $f14, $f12, $[[T2]] + ; CHECK: mov.s $f0, $f14 + %cond = icmp ne i32 %j, 0 + %res = select i1 %cond, float %k, float %l + ret float %res +} + define double @sel_double(i32 %j, double %k, double %l) { entry: ; CHECK-LABEL: sel_double: @@ -95,3 +109,18 @@ entry: %res = select i1 %cond, double %k, double %l ret double %res } + +define double @sel_double2(double %k, double %l, i32 %j) { +entry: + ; CHECK-LABEL: sel_double2: + + ; CHECK-DAG: lw $[[SEL:[0-9]+]], 16($sp) + ; CHECK-DAG: xor $[[T0:[0-9]+]], $[[SEL]], $zero + ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK: movn.d $f14, $f12, $[[T2]] + ; CHECK: mov.d $f0, $f14 + %cond = icmp ne i32 %j, 0 + %res = select i1 %cond, double %k, double %l + ret double %res +} |
