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authorAmara Emerson <aemerson@apple.com>2019-04-15 05:04:20 +0000
committerAmara Emerson <aemerson@apple.com>2019-04-15 05:04:20 +0000
commit946b1246d6c8fa95e827770e1d287184fc3dfd55 (patch)
tree7ac5551da962b92b876d9e37104ab3a5384291cd /llvm/test/CodeGen/Mips
parentd189680baa07e4ed6300cf07c18a1cd0ee5f4be9 (diff)
downloadbcm5719-llvm-946b1246d6c8fa95e827770e1d287184fc3dfd55.tar.gz
bcm5719-llvm-946b1246d6c8fa95e827770e1d287184fc3dfd55.zip
[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.
Other opcodes shouldn't be CSE'd until we can be sure debug info quality won't be degraded. This change also improves the IRTranslator so that in most places, but not all, it creates constants using the MIRBuilder directly instead of first creating a new destination vreg and then creating a constant. By doing this, the buildConstant() method can just return the vreg of an existing G_CONSTANT instead of having to create a COPY from it. I measured a 0.2% improvement in compile time and a 0.9% improvement in code size at -O0 ARM64. Compile time: Program base cse diff test-suite...ark/tramp3d-v4/tramp3d-v4.test 9.04 9.12 0.8% test-suite...Mark/mafft/pairlocalalign.test 2.68 2.66 -0.7% test-suite...-typeset/consumer-typeset.test 5.53 5.51 -0.4% test-suite :: CTMark/lencod/lencod.test 5.30 5.28 -0.3% test-suite :: CTMark/Bullet/bullet.test 25.82 25.76 -0.2% test-suite...:: CTMark/ClamAV/clamscan.test 6.92 6.90 -0.2% test-suite...TMark/7zip/7zip-benchmark.test 34.24 34.17 -0.2% test-suite :: CTMark/SPASS/SPASS.test 6.25 6.24 -0.1% test-suite...:: CTMark/sqlite3/sqlite3.test 1.66 1.66 -0.1% test-suite :: CTMark/kimwitu++/kc.test 13.61 13.60 -0.0% Geomean difference -0.2% Code size: Program base cse diff test-suite...-typeset/consumer-typeset.test 1315632 1266480 -3.7% test-suite...:: CTMark/ClamAV/clamscan.test 1313892 1297508 -1.2% test-suite :: CTMark/lencod/lencod.test 1439504 1423112 -1.1% test-suite...TMark/7zip/7zip-benchmark.test 2936980 2904172 -1.1% test-suite :: CTMark/Bullet/bullet.test 3478276 3445460 -0.9% test-suite...ark/tramp3d-v4/tramp3d-v4.test 8082868 8033492 -0.6% test-suite :: CTMark/kimwitu++/kc.test 3870380 3853972 -0.4% test-suite :: CTMark/SPASS/SPASS.test 1434904 1434896 -0.0% test-suite...Mark/mafft/pairlocalalign.test 764528 764528 0.0% test-suite...:: CTMark/sqlite3/sqlite3.test 782092 782092 0.0% Geomean difference -0.9% Differential Revision: https://reviews.llvm.org/D60580 llvm-svn: 358369
Diffstat (limited to 'llvm/test/CodeGen/Mips')
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir12
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir30
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir92
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir12
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll16
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll40
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll36
-rw-r--r--llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll20
8 files changed, 105 insertions, 153 deletions
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
index 35bb2bdaca8..9b2dcadef0f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -236,9 +236,8 @@ body: |
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[COPY3]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
; MIPS32: $v0 = COPY [[ADD3]](s32)
; MIPS32: $v1 = COPY [[ADD1]](s32)
@@ -291,21 +290,18 @@ body: |
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD1]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
- ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND2]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD5]](s32), [[LOAD2]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
- ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[AND3]]
; MIPS32: $v0 = COPY [[ADD1]](s32)
; MIPS32: $v1 = COPY [[ADD3]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
index d6c6114d374..7312f46e1b0 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
@@ -289,9 +289,8 @@ body: |
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
@@ -300,32 +299,27 @@ body: |
; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
- ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
- ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]]
; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
- ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ICMP5]](s32)
- ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]]
+ ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]]
; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]]
; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
- ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP6]](s32)
- ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]]
; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
@@ -393,29 +387,25 @@ body: |
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
- ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
- ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
index f722e8e46f0..cc31f068151 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
@@ -34,17 +34,15 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]]
- ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -71,17 +69,15 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]]
- ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -169,17 +165,15 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]]
- ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -206,17 +200,15 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]]
- ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -305,14 +297,13 @@ body: |
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]]
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -340,14 +331,13 @@ body: |
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]]
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -436,14 +426,13 @@ body: |
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]]
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -471,14 +460,13 @@ body: |
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]]
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]]
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
index 3b80ca090ed..b3f37916739 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
@@ -288,27 +288,23 @@ body: |
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]]
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]]
; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]]
; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
- ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]]
; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
- ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]]
; MIPS32: $v0 = COPY [[SUB]](s32)
; MIPS32: $v1 = COPY [[SUB2]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
index 57dbddc32bf..8a6571108d6 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
@@ -94,10 +94,9 @@ define i64 @add_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: sltu $2, $1, $6
-; MIPS32-NEXT: addu $3, $7, $5
-; MIPS32-NEXT: ori $4, $zero, 1
-; MIPS32-NEXT: and $2, $2, $4
-; MIPS32-NEXT: addu $3, $3, $2
+; MIPS32-NEXT: addu $4, $7, $5
+; MIPS32-NEXT: and $2, $2, $3
+; MIPS32-NEXT: addu $3, $4, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -126,18 +125,15 @@ define i128 @add_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: addu $4, $4, $9
; MIPS32-NEXT: sltu $1, $4, $1
; MIPS32-NEXT: addu $5, $2, $5
-; MIPS32-NEXT: ori $9, $zero, 1
-; MIPS32-NEXT: and $1, $1, $9
+; MIPS32-NEXT: and $1, $1, $10
; MIPS32-NEXT: addu $1, $5, $1
; MIPS32-NEXT: sltu $2, $1, $2
; MIPS32-NEXT: addu $5, $3, $6
-; MIPS32-NEXT: ori $6, $zero, 1
-; MIPS32-NEXT: and $2, $2, $6
+; MIPS32-NEXT: and $2, $2, $10
; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: sltu $3, $2, $3
; MIPS32-NEXT: addu $5, $8, $7
-; MIPS32-NEXT: ori $6, $zero, 1
-; MIPS32-NEXT: and $3, $3, $6
+; MIPS32-NEXT: and $3, $3, $10
; MIPS32-NEXT: addu $5, $5, $3
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $4
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
index 7e5fc781bfa..43b4b63f66e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
@@ -124,40 +124,34 @@ define i128 @mul_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: and $11, $11, $13
; MIPS32-NEXT: addu $10, $10, $12
; MIPS32-NEXT: sltu $12, $10, $12
-; MIPS32-NEXT: ori $13, $zero, 1
; MIPS32-NEXT: and $12, $12, $13
; MIPS32-NEXT: addu $11, $11, $12
; MIPS32-NEXT: mul $12, $3, $4
-; MIPS32-NEXT: mul $13, $2, $5
-; MIPS32-NEXT: mul $14, $1, $6
+; MIPS32-NEXT: mul $14, $2, $5
+; MIPS32-NEXT: mul $15, $1, $6
; MIPS32-NEXT: multu $2, $4
-; MIPS32-NEXT: mfhi $15
-; MIPS32-NEXT: multu $1, $5
; MIPS32-NEXT: mfhi $24
-; MIPS32-NEXT: addu $12, $12, $13
-; MIPS32-NEXT: sltu $13, $12, $13
-; MIPS32-NEXT: ori $25, $zero, 1
-; MIPS32-NEXT: and $13, $13, $25
+; MIPS32-NEXT: multu $1, $5
+; MIPS32-NEXT: mfhi $25
; MIPS32-NEXT: addu $12, $12, $14
; MIPS32-NEXT: sltu $14, $12, $14
-; MIPS32-NEXT: ori $25, $zero, 1
-; MIPS32-NEXT: and $14, $14, $25
-; MIPS32-NEXT: addu $13, $13, $14
+; MIPS32-NEXT: and $14, $14, $13
; MIPS32-NEXT: addu $12, $12, $15
-; MIPS32-NEXT: sltu $14, $12, $15
-; MIPS32-NEXT: ori $15, $zero, 1
-; MIPS32-NEXT: and $14, $14, $15
-; MIPS32-NEXT: addu $13, $13, $14
+; MIPS32-NEXT: sltu $15, $12, $15
+; MIPS32-NEXT: and $15, $15, $13
+; MIPS32-NEXT: addu $14, $14, $15
; MIPS32-NEXT: addu $12, $12, $24
-; MIPS32-NEXT: sltu $14, $12, $24
-; MIPS32-NEXT: ori $15, $zero, 1
-; MIPS32-NEXT: and $14, $14, $15
-; MIPS32-NEXT: addu $13, $13, $14
+; MIPS32-NEXT: sltu $15, $12, $24
+; MIPS32-NEXT: and $15, $15, $13
+; MIPS32-NEXT: addu $14, $14, $15
+; MIPS32-NEXT: addu $12, $12, $25
+; MIPS32-NEXT: sltu $15, $12, $25
+; MIPS32-NEXT: and $15, $15, $13
+; MIPS32-NEXT: addu $14, $14, $15
; MIPS32-NEXT: addu $12, $12, $11
; MIPS32-NEXT: sltu $11, $12, $11
-; MIPS32-NEXT: ori $14, $zero, 1
-; MIPS32-NEXT: and $11, $11, $14
-; MIPS32-NEXT: addu $11, $13, $11
+; MIPS32-NEXT: and $11, $11, $13
+; MIPS32-NEXT: addu $11, $14, $11
; MIPS32-NEXT: mul $8, $8, $4
; MIPS32-NEXT: mul $13, $3, $5
; MIPS32-NEXT: mul $14, $2, $6
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
index 33149feeeb8..7ce74bb68be 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
@@ -158,11 +158,10 @@ define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: udiv_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 255
-; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: ori $2, $zero, 255
-; MIPS32-NEXT: and $2, $4, $2
-; MIPS32-NEXT: divu $zero, $1, $2
-; MIPS32-NEXT: teq $2, $zero, 7
+; MIPS32-NEXT: and $2, $5, $1
+; MIPS32-NEXT: and $1, $4, $1
+; MIPS32-NEXT: divu $zero, $2, $1
+; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
@@ -177,11 +176,10 @@ define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: udiv_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 65535
-; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: ori $2, $zero, 65535
-; MIPS32-NEXT: and $2, $4, $2
-; MIPS32-NEXT: divu $zero, $1, $2
-; MIPS32-NEXT: teq $2, $zero, 7
+; MIPS32-NEXT: and $2, $5, $1
+; MIPS32-NEXT: and $1, $4, $1
+; MIPS32-NEXT: divu $zero, $2, $1
+; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
@@ -234,11 +232,10 @@ define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: urem_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 255
-; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: ori $2, $zero, 255
-; MIPS32-NEXT: and $2, $4, $2
-; MIPS32-NEXT: divu $zero, $1, $2
-; MIPS32-NEXT: teq $2, $zero, 7
+; MIPS32-NEXT: and $2, $5, $1
+; MIPS32-NEXT: and $1, $4, $1
+; MIPS32-NEXT: divu $zero, $2, $1
+; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
@@ -253,11 +250,10 @@ define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: urem_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 65535
-; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: ori $2, $zero, 65535
-; MIPS32-NEXT: and $2, $4, $2
-; MIPS32-NEXT: divu $zero, $1, $2
-; MIPS32-NEXT: teq $2, $zero, 7
+; MIPS32-NEXT: and $2, $5, $1
+; MIPS32-NEXT: and $1, $4, $1
+; MIPS32-NEXT: divu $zero, $2, $1
+; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
index 7e96449571f..0a15f673b66 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
@@ -117,27 +117,23 @@ define i128 @sub_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: sltu $1, $1, $4
; MIPS32-NEXT: subu $4, $2, $5
; MIPS32-NEXT: ori $10, $zero, 1
-; MIPS32-NEXT: and $10, $1, $10
-; MIPS32-NEXT: subu $4, $4, $10
-; MIPS32-NEXT: xor $10, $2, $5
-; MIPS32-NEXT: sltiu $10, $10, 1
+; MIPS32-NEXT: and $11, $1, $10
+; MIPS32-NEXT: subu $4, $4, $11
+; MIPS32-NEXT: xor $11, $2, $5
+; MIPS32-NEXT: sltiu $11, $11, 1
; MIPS32-NEXT: sltu $2, $2, $5
-; MIPS32-NEXT: ori $5, $zero, 1
-; MIPS32-NEXT: and $5, $10, $5
+; MIPS32-NEXT: and $5, $11, $10
; MIPS32-NEXT: movn $2, $1, $5
; MIPS32-NEXT: subu $1, $3, $6
-; MIPS32-NEXT: ori $5, $zero, 1
-; MIPS32-NEXT: and $5, $2, $5
+; MIPS32-NEXT: and $5, $2, $10
; MIPS32-NEXT: subu $1, $1, $5
; MIPS32-NEXT: xor $5, $3, $6
; MIPS32-NEXT: sltiu $5, $5, 1
; MIPS32-NEXT: sltu $3, $3, $6
-; MIPS32-NEXT: ori $6, $zero, 1
-; MIPS32-NEXT: and $5, $5, $6
+; MIPS32-NEXT: and $5, $5, $10
; MIPS32-NEXT: movn $3, $2, $5
; MIPS32-NEXT: subu $2, $8, $7
-; MIPS32-NEXT: ori $5, $zero, 1
-; MIPS32-NEXT: and $3, $3, $5
+; MIPS32-NEXT: and $3, $3, $10
; MIPS32-NEXT: subu $5, $2, $3
; MIPS32-NEXT: move $2, $9
; MIPS32-NEXT: move $3, $4
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