[MIPS GlobalISel] Select add i32, i32

Add the minimal support necessary to lower a function that returns the
sum of two i32 values.
Support argument/return lowering of i32 values through registers only.
Add tablegen for regbankselect and instructionselect.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D44304

llvm-svn: 329819

5 files changed, 131 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
new file mode 100644
index 00000000000..14a1503796d
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @add_i32(i32 %x, i32 %y) {entry: ret void}
+
+...
+---
+name:            add_i32
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: add_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[ADDu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = G_ADD %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
new file mode 100644
index 00000000000..9884b996ce0
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/add.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+define i32 @add_i32(i32 %x, i32 %y) {
+  ; MIPS32-LABEL: name: add_i32
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+  ; MIPS32:   $v0 = COPY [[ADD]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %z = add i32 %x, %y
+  ret i32 %z
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
new file mode 100644
index 00000000000..d87a97d9a6f
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @add_i32(i32 %x, i32 %y) {entry: ret void}
+
+...
+---
+name:            add_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: add_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[ADD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_ADD %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
new file mode 100644
index 00000000000..a08035799fb
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
@@ -0,0 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+define i32 @add_i32(i32 %x, i32 %y) {
+; MIPS32-LABEL: add_i32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addu $2, $4, $5
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %z = add i32 %x, %y
+  ret i32 %z
+}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
new file mode 100644
index 00000000000..b7b122ac071
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @add_i32(i32 %x, i32 %y) {entry: ret void}
+
+...
+---
+name:            add_i32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: add_i32
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
+    ; MIPS32: $v0 = COPY [[ADD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = G_ADD %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...