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authorReed Kotler <rkotler@mips.com>2012-10-23 01:35:48 +0000
committerReed Kotler <rkotler@mips.com>2012-10-23 01:35:48 +0000
commit164bb37c7be710a07879ebe9711da0229aa18021 (patch)
tree14195877a5fa268afa4eae10bfa32575294b714b /llvm/test/CodeGen/Mips
parent7ccb6d9f8a655f1d32f6b4f87d40838a4eabfbc5 (diff)
downloadbcm5719-llvm-164bb37c7be710a07879ebe9711da0229aa18021.tar.gz
bcm5719-llvm-164bb37c7be710a07879ebe9711da0229aa18021.zip
implement setXX patterns
llvm-svn: 166459
Diffstat (limited to 'llvm/test/CodeGen/Mips')
-rw-r--r--llvm/test/CodeGen/Mips/seteq.ll21
-rw-r--r--llvm/test/CodeGen/Mips/seteqz.ll24
-rw-r--r--llvm/test/CodeGen/Mips/setge.ll27
-rw-r--r--llvm/test/CodeGen/Mips/setgek.ll18
-rw-r--r--llvm/test/CodeGen/Mips/setle.ll26
-rw-r--r--llvm/test/CodeGen/Mips/setlt.ll21
-rw-r--r--llvm/test/CodeGen/Mips/setltk.ll20
-rw-r--r--llvm/test/CodeGen/Mips/setne.ll20
-rw-r--r--llvm/test/CodeGen/Mips/setuge.ll26
-rw-r--r--llvm/test/CodeGen/Mips/setugt.ll21
-rw-r--r--llvm/test/CodeGen/Mips/setule.ll26
-rw-r--r--llvm/test/CodeGen/Mips/setult.ll21
-rw-r--r--llvm/test/CodeGen/Mips/setultk.ll20
13 files changed, 291 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/seteq.ll b/llvm/test/CodeGen/Mips/seteq.ll
new file mode 100644
index 00000000000..da840c83a2b
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/seteq.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@i = global i32 1, align 4
+@j = global i32 10, align 4
+@k = global i32 1, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @i, align 4
+ %1 = load i32* @k, align 4
+ %cmp = icmp eq i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; 16: move ${{[0-9]+}}, $t8
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/Mips/seteqz.ll b/llvm/test/CodeGen/Mips/seteqz.ll
new file mode 100644
index 00000000000..d445be6aedb
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/seteqz.ll
@@ -0,0 +1,24 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@i = global i32 0, align 4
+@j = global i32 99, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @i, align 4
+ %cmp = icmp eq i32 %0, 0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: sltiu ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $t8
+ %1 = load i32* @j, align 4
+ %cmp1 = icmp eq i32 %1, 99
+ %conv2 = zext i1 %cmp1 to i32
+ store i32 %conv2, i32* @r2, align 4
+; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; 16: move ${{[0-9]+}}, $t8
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setge.ll b/llvm/test/CodeGen/Mips/setge.ll
new file mode 100644
index 00000000000..94b499bc31e
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setge.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 -5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+@.str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @k, align 4
+ %1 = load i32* @j, align 4
+ %cmp = icmp sge i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $t8
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
+ %2 = load i32* @m, align 4
+ %cmp1 = icmp sge i32 %0, %2
+ %conv2 = zext i1 %cmp1 to i32
+ store i32 %conv2, i32* @r2, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setgek.ll b/llvm/test/CodeGen/Mips/setgek.ll
new file mode 100644
index 00000000000..40aaa7c0302
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setgek.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@k = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @k, align 4
+ %cmp = icmp sgt i32 %0, -32769
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: slti ${{[0-9]+}}, -32768
+; 16: move $[[REGISTER:[0-9]+]], $t8
+; 16: xor ${{[0-9]+}}, $[[REGISTER]]
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setle.ll b/llvm/test/CodeGen/Mips/setle.ll
new file mode 100644
index 00000000000..f36fb4392d7
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setle.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 -5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @j, align 4
+ %1 = load i32* @k, align 4
+ %cmp = icmp sle i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $t8
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
+ %2 = load i32* @m, align 4
+ %cmp1 = icmp sle i32 %2, %1
+ %conv2 = zext i1 %cmp1 to i32
+ store i32 %conv2, i32* @r2, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setlt.ll b/llvm/test/CodeGen/Mips/setlt.ll
new file mode 100644
index 00000000000..435be8e2334
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setlt.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 -5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @j, align 4
+ %1 = load i32* @k, align 4
+ %cmp = icmp slt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $t8
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setltk.ll b/llvm/test/CodeGen/Mips/setltk.ll
new file mode 100644
index 00000000000..c0b610e3778
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setltk.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 -5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @j, align 4
+ %cmp = icmp slt i32 %0, 10
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: slti $[[REGISTER:[0-9]+]], 10
+; 16: move $[[REGISTER]], $t8
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setne.ll b/llvm/test/CodeGen/Mips/setne.ll
new file mode 100644
index 00000000000..6460c83c7b0
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setne.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@i = global i32 1, align 4
+@j = global i32 10, align 4
+@k = global i32 1, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @i, align 4
+ %1 = load i32* @k, align 4
+ %cmp = icmp ne i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
+; 16: move ${{[0-9]+}}, $t8
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setuge.ll b/llvm/test/CodeGen/Mips/setuge.ll
new file mode 100644
index 00000000000..ac72b66e9fb
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setuge.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @k, align 4
+ %1 = load i32* @j, align 4
+ %cmp = icmp uge i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $t8
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
+ %2 = load i32* @m, align 4
+ %cmp1 = icmp uge i32 %0, %2
+ %conv2 = zext i1 %cmp1 to i32
+ store i32 %conv2, i32* @r2, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setugt.ll b/llvm/test/CodeGen/Mips/setugt.ll
new file mode 100644
index 00000000000..328f0e3be34
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setugt.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @k, align 4
+ %1 = load i32* @j, align 4
+ %cmp = icmp ugt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $t8
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setule.ll b/llvm/test/CodeGen/Mips/setule.ll
new file mode 100644
index 00000000000..792f2ae0fa2
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setule.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @j, align 4
+ %1 = load i32* @k, align 4
+ %cmp = icmp ule i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $t8
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
+ %2 = load i32* @m, align 4
+ %cmp1 = icmp ule i32 %2, %1
+ %conv2 = zext i1 %cmp1 to i32
+ store i32 %conv2, i32* @r2, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setult.ll b/llvm/test/CodeGen/Mips/setult.ll
new file mode 100644
index 00000000000..56d2e8daa3e
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setult.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @j, align 4
+ %1 = load i32* @k, align 4
+ %cmp = icmp ult i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $t8
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/setultk.ll b/llvm/test/CodeGen/Mips/setultk.ll
new file mode 100644
index 00000000000..75b270ed842
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/setultk.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+@j = global i32 5, align 4
+@k = global i32 10, align 4
+@l = global i32 20, align 4
+@m = global i32 10, align 4
+@r1 = common global i32 0, align 4
+@r2 = common global i32 0, align 4
+@r3 = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @j, align 4
+ %cmp = icmp ult i32 %0, 10
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @r1, align 4
+; 16: sltiu $[[REGISTER:[0-9]+]], 10
+; 16: move $[[REGISTER]], $t8
+ ret void
+}
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