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| author | Simon Atanasyan <simon@atanasyan.com> | 2018-07-21 16:16:03 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2018-07-21 16:16:03 +0000 |
| commit | ecd1e0afdd30c136689c13b5b5ef16482b718753 (patch) | |
| tree | bc7eaecfa4cd42c670ed4af03d2357b85f776109 /llvm/test/CodeGen/Mips/tls.ll | |
| parent | c93b870c54303806371ba9132af686e88e256a78 (diff) | |
| download | bcm5719-llvm-ecd1e0afdd30c136689c13b5b5ef16482b718753.tar.gz bcm5719-llvm-ecd1e0afdd30c136689c13b5b5ef16482b718753.zip | |
[mips] Move out the WrapperPat declaration from the NotInMicroMips predicate
This is a follow-up to the rL335185. Those commit adds some WrapperPat
patterns for microMIPS target. But declaration of the WrapperPat class
is under the NotInMicroMips predicate and microMIPS patterns cannot be
selected because predicate (Subtarget->inMicroMipsMode()) &&
(!Subtarget->inMicroMipsMode()) is always false.
This change move out the WrapperPat class declaration from the
NotInMicroMips predicate and enables microMIPS WrapperPat patterns.
Differential revision: https://reviews.llvm.org/D49533
llvm-svn: 337646
Diffstat (limited to 'llvm/test/CodeGen/Mips/tls.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/tls.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/tls.ll b/llvm/test/CodeGen/Mips/tls.ll index b416f1f6a5e..b3905d86ea4 100644 --- a/llvm/test/CodeGen/Mips/tls.ll +++ b/llvm/test/CodeGen/Mips/tls.ll @@ -1,5 +1,7 @@ ; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=PIC,CHECK +; RUN: llc -mtriple=mipsel-- -mattr=+micromips -disable-mips-delay-filler \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=MM,CHECK ; RUN: llc -mtriple=mipsel-- -relocation-model=static -disable-mips-delay-filler < \ ; RUN: %s | FileCheck %s -check-prefixes=STATIC,CHECK ; RUN: llc -mtriple=mipsel-- -relocation-model=static -disable-mips-delay-filler \ @@ -20,6 +22,13 @@ entry: ; PIC-DAG: jalr $25 ; PIC-DAG: lw $2, 0($2) +; MM-LABEL: f1: +; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25 +; MM-DAG: lw $25, %call16(__tls_get_addr)($[[R0]]) +; MM-DAG: addiu $4, $[[R0]], %tlsgd(t1) +; MM-DAG: jalr $25 +; MM-DAG: lw16 $2, 0($2) + ; STATIC-LABEL: f1: ; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1) ; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) @@ -43,6 +52,13 @@ entry: ; PIC-DAG: jalr $25 ; PIC-DAG: lw $2, 0($2) +; MM-LABEL: f2: +; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25 +; MM-DAG: lw $25, %call16(__tls_get_addr)($[[R0]]) +; MM-DAG: addiu $4, $[[R0]], %tlsgd(t2) +; MM-DAG: jalr $25 +; MM-DAG: lw16 $2, 0($2) + ; STATICGP-LABEL: f2: ; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) ; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) @@ -69,6 +85,12 @@ entry: ; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2 ; PIC: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]]) +; MM: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i) +; MM: jalr $25 +; MM: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i) +; MM: addu16 $[[R1:[0-9]+]], $[[R0]], $2 +; MM: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]]) + %0 = load i32, i32* @f3.i, align 4 %inc = add nsw i32 %0, 1 store i32 %inc, i32* @f3.i, align 4 |
