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| author | Reed Kotler <rkotler@mips.com> | 2013-02-21 04:22:38 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-02-21 04:22:38 +0000 |
| commit | 97ba5f277202999521f9f94aefce1ad6496dc0dc (patch) | |
| tree | d7152252e530709253ff6817e29ae3fe4576bc92 /llvm/test/CodeGen/Mips/selpat.ll | |
| parent | dff95876407c9f3f12afadefef981102b14cb8ca (diff) | |
| download | bcm5719-llvm-97ba5f277202999521f9f94aefce1ad6496dc0dc.tar.gz bcm5719-llvm-97ba5f277202999521f9f94aefce1ad6496dc0dc.zip | |
Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.
llvm-svn: 175718
Diffstat (limited to 'llvm/test/CodeGen/Mips/selpat.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/selpat.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/Mips/selpat.ll b/llvm/test/CodeGen/Mips/selpat.ll index cda0c96ef4b..57cc126bed1 100644 --- a/llvm/test/CodeGen/Mips/selpat.ll +++ b/llvm/test/CodeGen/Mips/selpat.ll @@ -67,7 +67,7 @@ entry: %2 = load i32* @f, align 4 %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: beqz ${{[0-9]+}}, .+4 +; 16: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp eq i32 %3, 0 @@ -238,7 +238,7 @@ entry: %2 = load i32* @t, align 4 %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: bnez ${{[0-9]+}}, .+4 +; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp ne i32 %3, 0 @@ -260,7 +260,7 @@ entry: %2 = load i32* @t, align 4 %cond = select i1 %tobool, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: bnez ${{[0-9]+}}, .+4 +; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %tobool1 = icmp ne i32 %3, 0 |
