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| author | Chuang-Yu Cheng <cycheng@multicorewareinc.com> | 2016-04-05 14:06:20 +0000 |
|---|---|---|
| committer | Chuang-Yu Cheng <cycheng@multicorewareinc.com> | 2016-04-05 14:06:20 +0000 |
| commit | d3fb38cae5227d9c23a2be5562b5f22c469c1b71 (patch) | |
| tree | 343da88cf78baf1a91bb76c7d2b159589c4996d2 /llvm/test/CodeGen/Mips/prevent-hoisting.ll | |
| parent | a0beb762a4d33cdbee86d3f0fa6d6d0efd37a99f (diff) | |
| download | bcm5719-llvm-d3fb38cae5227d9c23a2be5562b5f22c469c1b71.tar.gz bcm5719-llvm-d3fb38cae5227d9c23a2be5562b5f22c469c1b71.zip | |
Don't delete empty preheaders in CodeGenPrepare if it would create a critical edge
Presently, CodeGenPrepare deletes all nearly empty (only phi and branch)
basic blocks. This pass can delete loop preheaders which frequently creates
critical edges. A preheader can be a convenient place to spill registers to
the stack. If the entrance to a loop body is a critical edge, then spills
may occur in the loop body rather than immediately before it. This patch
protects loop preheaders from deletion in CodeGenPrepare even if they are
nearly empty.
Since the patch alters the CFG, it affects a large number of test cases.
In most cases, the changes are merely cosmetic (basic blocks have different
names or instruction orders change slightly). I am somewhat concerned about
the test/CodeGen/Mips/brdelayslot.ll test case. If the loop preheader is not
deleted, then the MIPS backend does not take advantage of a branch delay
slot. Consequently, I would like some close review by a MIPS expert.
The patch also partially subsumes D16893 from George Burgess IV. George
correctly notes that CodeGenPrepare does not actually preserve the dominator
tree. I think the dominator tree was usually not valid when CodeGenPrepare
ran, but I am using LoopInfo to mark preheaders, so the dominator tree is
now always valid before CodeGenPrepare.
Author: Tom Jablin (tjablin)
Reviewers: hfinkel george.burgess.iv vkalintiris dsanders kbarton cycheng
http://reviews.llvm.org/D16984
llvm-svn: 265397
Diffstat (limited to 'llvm/test/CodeGen/Mips/prevent-hoisting.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/prevent-hoisting.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/Mips/prevent-hoisting.ll b/llvm/test/CodeGen/Mips/prevent-hoisting.ll index 81b14d7441b..696147ba171 100644 --- a/llvm/test/CodeGen/Mips/prevent-hoisting.ll +++ b/llvm/test/CodeGen/Mips/prevent-hoisting.ll @@ -11,12 +11,12 @@ ; CHECK-LABEL: readLumaCoeff8x8_CABAC ; The check for first "addiu" instruction is added so that we can match the correct "b" instruction. -; CHECK: addiu ${{[0-9]+}}, $zero, -1 +; CHECK: andi ; CHECK: b $[[BB0:BB[0-9_]+]] -; CHECK-NEXT: addiu ${{[0-9]+}}, $zero, 0 +; CHECK-NEXT: sll ; Check that at the start of a fallthrough block there is a instruction that writes to $1. -; CHECK-NEXT: {{BB[0-9_#]+}}: +; CHECK-NEXT: {{BB[0-9_#]+}}: ; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) ; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4 |
