diff options
| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-09 15:48:05 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-09 15:48:05 +0000 |
| commit | 623282f0dd7fb1dba7623f2b10294f003f92570e (patch) | |
| tree | 50ef8579d1ec548ed23c7b26ddd95254dcba78d4 /llvm/test/CodeGen/Mips/msa/bit.ll | |
| parent | 901d91e5f0f5dc1c449b60b97af1adaf5c928eb9 (diff) | |
| download | bcm5719-llvm-623282f0dd7fb1dba7623f2b10294f003f92570e.tar.gz bcm5719-llvm-623282f0dd7fb1dba7623f2b10294f003f92570e.zip | |
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.
llvm-svn: 365507
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/bit.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/bit.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll index f0057307bbf..2a4632f0807 100644 --- a/llvm/test/CodeGen/Mips/msa/bit.ll +++ b/llvm/test/CodeGen/Mips/msa/bit.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the BIT instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 |
