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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-15 11:04:16 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-11-15 11:04:16 +0000 |
| commit | 1ede3002fa9c005b69fb25671c336e71c672c009 (patch) | |
| tree | 1c43b4f752f008e8ed17d5c21a462f760342b8e5 /llvm/test/CodeGen/Mips/msa/basic_operations.ll | |
| parent | a6e8322fb1e57df5d2d1bd4833e66853446d4879 (diff) | |
| download | bcm5719-llvm-1ede3002fa9c005b69fb25671c336e71c672c009.tar.gz bcm5719-llvm-1ede3002fa9c005b69fb25671c336e71c672c009.zip | |
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.
Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConstant() produces illegal types. These have been temporarily
marked XFAIL and the XFAIL flag will be removed when
SelectionDAG::getConstant() is fixed.
There are three categories of failure:
* Immediate instructions are not selected in one endian mode.
* Immediates used in ldi.[bhwd] must be different according to endianness.
(this only affects cases where the 'wrong' ldi is used to load the correct
bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...)))
* Non-immediate instructions that rely on immediates affected by the
previous two categories as part of their match pattern.
For example, the bset match pattern is the vector equivalent of
'ws | (1 << wt)'.
One test needed correcting to expect different output depending on whether big
or little endian was in use. This test was
test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category
of failure shown above. The little endian version of this test is named
basic_operations_little.ll and will be merged back into basic_operations.ll in
a follow up commit now that FileCheck supports multiple check prefixes.
Reviewers: bkramer, jacksprat, dsanders
Reviewed By: dsanders
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1972
llvm-svn: 194806
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/basic_operations.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/basic_operations.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll index 73c17dc468b..2f153bfdfe9 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll @@ -22,8 +22,8 @@ define void @const_v16i8() nounwind { store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8 ; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo( - store volatile <16 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2>, <16 x i8>*@v16i8 - ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 258 + store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8 + ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 256 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8 ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 258 |
