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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
| commit | 1b1e25b7c51a4f021050cd693f77dc9d4a84740f (patch) | |
| tree | 211f908076cebe1b5d93f3bd3dacd0fb618d9375 /llvm/test/CodeGen/Mips/msa/3rf_float_int.ll | |
| parent | db4c21f9945283f2e8d29c7a8a898512ebf37b52 (diff) | |
| download | bcm5719-llvm-1b1e25b7c51a4f021050cd693f77dc9d4a84740f.tar.gz bcm5719-llvm-1b1e25b7c51a4f021050cd693f77dc9d4a84740f.zip | |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
llvm-svn: 191498
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/3rf_float_int.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/3rf_float_int.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll index 6fd46f5e7f2..a446ebd0b78 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; take an integer as an operand. -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 |
