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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-09 15:48:05 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-09 15:48:05 +0000 |
| commit | 623282f0dd7fb1dba7623f2b10294f003f92570e (patch) | |
| tree | 50ef8579d1ec548ed23c7b26ddd95254dcba78d4 /llvm/test/CodeGen/Mips/msa/2rf_int_float.ll | |
| parent | 901d91e5f0f5dc1c449b60b97af1adaf5c928eb9 (diff) | |
| download | bcm5719-llvm-623282f0dd7fb1dba7623f2b10294f003f92570e.tar.gz bcm5719-llvm-623282f0dd7fb1dba7623f2b10294f003f92570e.zip | |
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.
llvm-svn: 365507
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/2rf_int_float.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/2rf_int_float.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll index f845f3ddd74..8aeafded89e 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 |
