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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll index 64e459e4d9a..ddcd3cf757d 100644 --- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -15,7 +15,7 @@ define void @llvm_mips_fill_b_test() nounwind { entry: - %0 = load i32* @llvm_mips_fill_b_ARG1 + %0 = load i32, i32* @llvm_mips_fill_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0) store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES ret void @@ -35,7 +35,7 @@ declare <16 x i8> @llvm.mips.fill.b(i32) nounwind define void @llvm_mips_fill_h_test() nounwind { entry: - %0 = load i32* @llvm_mips_fill_h_ARG1 + %0 = load i32, i32* @llvm_mips_fill_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0) store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES ret void @@ -55,7 +55,7 @@ declare <8 x i16> @llvm.mips.fill.h(i32) nounwind define void @llvm_mips_fill_w_test() nounwind { entry: - %0 = load i32* @llvm_mips_fill_w_ARG1 + %0 = load i32, i32* @llvm_mips_fill_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0) store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES ret void @@ -75,7 +75,7 @@ declare <4 x i32> @llvm.mips.fill.w(i32) nounwind define void @llvm_mips_fill_d_test() nounwind { entry: - %0 = load i64* @llvm_mips_fill_d_ARG1 + %0 = load i64, i64* @llvm_mips_fill_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0) store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES ret void |
