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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-27 10:08:31 +0000 |
| commit | 1b1e25b7c51a4f021050cd693f77dc9d4a84740f (patch) | |
| tree | 211f908076cebe1b5d93f3bd3dacd0fb618d9375 /llvm/test/CodeGen/Mips/msa/2r.ll | |
| parent | db4c21f9945283f2e8d29c7a8a898512ebf37b52 (diff) | |
| download | bcm5719-llvm-1b1e25b7c51a4f021050cd693f77dc9d4a84740f.tar.gz bcm5719-llvm-1b1e25b7c51a4f021050cd693f77dc9d4a84740f.zip | |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
llvm-svn: 191498
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/2r.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/2r.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll index 7719b7cc0cf..9a3189b126a 100644 --- a/llvm/test/CodeGen/Mips/msa/2r.ll +++ b/llvm/test/CodeGen/Mips/msa/2r.ll @@ -1,6 +1,6 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 |
