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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-09-30 02:08:54 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-09-30 02:08:54 +0000 |
| commit | 7769a777103dade80510141047d971baf8081fce (patch) | |
| tree | a1b3c12a762f8e8a81288e163180091827875e6a /llvm/test/CodeGen/Mips/mips64instrs.ll | |
| parent | 8d4c8e14988c774a502bd6d58a8df66f2a2f9e86 (diff) | |
| download | bcm5719-llvm-7769a777103dade80510141047d971baf8081fce.tar.gz bcm5719-llvm-7769a777103dade80510141047d971baf8081fce.zip | |
Mips64 arithmetic and logical instructions with one source register and
immediate.
llvm-svn: 140839
Diffstat (limited to 'llvm/test/CodeGen/Mips/mips64instrs.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/mips64instrs.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/mips64instrs.ll b/llvm/test/CodeGen/Mips/mips64instrs.ll index 1adf1379f68..8cbb5b947e4 100644 --- a/llvm/test/CodeGen/Mips/mips64instrs.ll +++ b/llvm/test/CodeGen/Mips/mips64instrs.ll @@ -34,3 +34,39 @@ entry: %xor = xor i64 %a1, %a0 ret i64 %xor } + +define i64 @f7(i64 %a0) nounwind readnone { +entry: +; CHECK: daddiu + %add = add nsw i64 %a0, 20 + ret i64 %add +} + +define i64 @f8(i64 %a0) nounwind readnone { +entry: +; CHECK: daddiu + %sub = add nsw i64 %a0, -20 + ret i64 %sub +} + +define i64 @f9(i64 %a0) nounwind readnone { +entry: +; CHECK: andi + %and = and i64 %a0, 20 + ret i64 %and +} + +define i64 @f10(i64 %a0) nounwind readnone { +entry: +; CHECK: ori + %or = or i64 %a0, 20 + ret i64 %or +} + +define i64 @f11(i64 %a0) nounwind readnone { +entry: +; CHECK: xori + %xor = xor i64 %a0, 20 + ret i64 %xor +} + |
