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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-01-12 15:15:14 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-01-12 15:15:14 +0000 |
| commit | 5e1d5a789a0e95befc19bbcf267d2646fb3eb21b (patch) | |
| tree | 93489adbc070f7ba232055cb56c6d29f35145ab4 /llvm/test/CodeGen/Mips/madd-msub.ll | |
| parent | b5b5a1d7ad3ab3746bf133d899325b51bed3bf16 (diff) | |
| download | bcm5719-llvm-5e1d5a789a0e95befc19bbcf267d2646fb3eb21b.tar.gz bcm5719-llvm-5e1d5a789a0e95befc19bbcf267d2646fb3eb21b.zip | |
[mips] Correct operand order in DSP's mthi/mtlo
Summary: The result register is the second operand as per the other mt* instructions.
Reviewers: vkalintiris
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D15993
llvm-svn: 257478
Diffstat (limited to 'llvm/test/CodeGen/Mips/madd-msub.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/madd-msub.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/Mips/madd-msub.ll b/llvm/test/CodeGen/Mips/madd-msub.ll index b84d94d3149..667676de5f3 100644 --- a/llvm/test/CodeGen/Mips/madd-msub.ll +++ b/llvm/test/CodeGen/Mips/madd-msub.ll @@ -18,7 +18,7 @@ ; 32-DAG: [[m]]flo $3 ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31 -; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6 +; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] ; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}} ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] @@ -64,7 +64,7 @@ entry: ; 32-DAG: [[m]]flo $3 ; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6 +; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] ; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}} ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] @@ -101,8 +101,8 @@ entry: ; 32-DAG: [[m]]fhi $2 ; 32-DAG: [[m]]flo $3 -; DSP-DAG: mthi $[[AC:ac[0-3]+]], $6 -; DSP-DAG: mtlo $[[AC]], $7 +; DSP-DAG: mthi $6, $[[AC:ac[0-3]+]] +; DSP-DAG: mtlo $7, $[[AC]] ; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}} ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] @@ -143,7 +143,7 @@ entry: ; 32-DAG: [[m]]flo $3 ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31 -; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6 +; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] ; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}} ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] @@ -189,7 +189,7 @@ entry: ; 32-DAG: [[m]]flo $3 ; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6 +; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] ; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}} ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] @@ -229,7 +229,7 @@ entry: ; 32-DAG: [[m]]flo $3 ; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6 +; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] ; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}} ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] |
