[Mips] Add support to match more patterns for DEXT and CINS

This patch adds support for recognizing more patterns to match to DEXT and
CINS instructions.
It finds cases where multiple instructions could be replaced with a single
DEXT or CINS instruction.

For example, for the following:

define i64 @dext_and32(i64 zeroext %a) {
entry:

 %and = and i64 %a, 4294967295
 ret i64 %and
}

instead of generating:

 0000000000000088 <dext_and32>:

 88:   64010001        daddiu  at,zero,1
 8c:   0001083c        dsll32  at,at,0x0
 90:   6421ffff        daddiu  at,at,-1
 94:   03e00008        jr      ra
 98:   00811024        and     v0,a0,at
 9c:   00000000        nop

the following gets generated:

 0000000000000068 <dext_and32>:

 68:   03e00008        jr      ra
 6c:   7c82f803        dext    v0,a0,0x0,0x20

Cases that are covered:

DEXT:

 1. and $src, mask where mask > 0xffff
 2. zext $src zero extend from i32 to i64

CINS:

 1. and (shl $src, pos), mask
 2. shl (and $src, mask), pos
 3. zext (shl $src, pos) zero extend from i32 to i64

Patch by Violeta Vukobrat.

Differential Revision: https://reviews.llvm.org/D30464

llvm-svn: 297832

1 files changed, 91 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll
index 6def55cf883..b998772d367 100644
--- a/llvm/test/CodeGen/Mips/load-store-left-right.ll
+++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll
@@ -8,8 +8,8 @@
 ; RUN: llc -march=mips64   -mcpu=mips4    -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
 ; RUN: llc -march=mips64el -mcpu=mips64   -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s
 ; RUN: llc -march=mips64   -mcpu=mips64   -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s
-; RUN: llc -march=mips64   -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EL %s
+; RUN: llc -march=mips64   -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EB %s
 ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EL %s
 ; RUN: llc -march=mips64   -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EB %s
 
@@ -37,9 +37,15 @@ entry:
 ; MIPS64-EL:     lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
 ; MIPS64-EL:     lwr $[[R0]], 0($[[R1]])
 
+; MIPS64R2-EL:   lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
+; MIPS64R2-EL:   lwr $[[R0]], 0($[[R1]])
+
 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
 
+; MIPS64R2-EB:   lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   lwr $[[R0]], 3($[[R1]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      lw $2, 0($[[PTR]])
 
@@ -63,9 +69,15 @@ entry:
 ; MIPS64-EL:     swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
 ; MIPS64-EL:     swr $[[R0]], 0($[[R1]])
 
+; MIPS64R2-EL:   swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
+; MIPS64R2-EL:   swr $[[R0]], 0($[[R1]])
+
 ; MIPS64-EB:     swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     swr $[[R0]], 3($[[R1]])
 
+; MIPS64R2-EB:   swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   swr $[[R0]], 3($[[R1]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      sw $4, 0($[[PTR]])
 
@@ -94,9 +106,15 @@ entry:
 ; MIPS64-EL:     ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
 ; MIPS64-EL:     ldr $[[R0]], 0($[[R1]])
 
+; MIPS64R2-EL:   ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
+; MIPS64R2-EL:   ldr $[[R0]], 0($[[R1]])
+
 ; MIPS64-EB:     ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     ldr $[[R0]], 7($[[R1]])
 
+; MIPS64R2-EB:   ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   ldr $[[R0]], 7($[[R1]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sll)(
 ; MIPS64R6:      ld $2, 0($[[PTR]])
 
@@ -123,9 +141,15 @@ entry:
 ; MIPS64-EL:     lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
 ; MIPS64-EL:     lwr $[[R0]], 0($[[R1]])
 
+; MIPS64R2-EL:   lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
+; MIPS64R2-EL:   lwr $[[R0]], 0($[[R1]])
+
 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
 
+; MIPS64R2-EB:   lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   lwr $[[R0]], 3($[[R1]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      lw $2, 0($[[PTR]])
 
@@ -159,9 +183,17 @@ entry:
 ; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1
 ; MIPS64-EL-DAG: and    ${{[0-9]+}}, $[[R0]], $[[R4]]
 
+; MIPS64R2-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
+; MIPS64R2-EL-DAG: lwr $[[R0]], 0($[[R1]])
+; MIPS64R2-EL-DAG: dext $[[R0]], $[[R0]], 0, 32
+
 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
 
+; MIPS64R2-EB:   lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   lwr $[[R0]], 3($[[R1]])
+; MIPS64R2-EB:   dext $[[R0]], $[[R0]], 0, 32
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sui)(
 ; MIPS64R6:      lwu $2, 0($[[PTR]])
 
@@ -191,9 +223,15 @@ entry:
 ; MIPS64-EL:     sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
 ; MIPS64-EL:     sdr $[[R0]], 0($[[R1]])
 
+; MIPS64R2-EL:   sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
+; MIPS64R2-EL:   sdr $[[R0]], 0($[[R1]])
+
 ; MIPS64-EB:     sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     sdr $[[R0]], 7($[[R1]])
 
+; MIPS64R2-EB:   sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   sdr $[[R0]], 7($[[R1]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sll)(
 ; MIPS64R6:      sd $4, 0($[[PTR]])
 
@@ -217,9 +255,15 @@ entry:
 ; MIPS64-EL:     swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
 ; MIPS64-EL:     swr $[[R0]], 0($[[R1]])
 
+; MIPS64R2-EL:   swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
+; MIPS64R2-EL:   swr $[[R0]], 0($[[R1]])
+
 ; MIPS64-EB:     swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     swr $[[R0]], 3($[[R1]])
 
+; MIPS64R2-EB:   swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
+; MIPS64R2-EB:   swr $[[R0]], 3($[[R1]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(si)(
 ; MIPS64R6:      sw $4, 0($[[PTR]])
 
@@ -247,7 +291,9 @@ entry:
 ; MIPS32-EB:     lw $[[PTR:[0-9]+]], %got(struct_s0)(
 ; MIPS32R6:      lw $[[PTR:[0-9]+]], %got(struct_s0)(
 ; MIPS64-EL:     ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
+; MIPS64R2-EL:   ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
 ; MIPS64-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
+; MIPS64R2-EB:   ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
 
 ; MIPS32-DAG:       lbu $[[R1:[0-9]+]], 0($[[PTR]])
@@ -297,18 +343,29 @@ entry:
 ; MIPS32R6-DAG:  sw $[[R1]], 4($[[PTR]])
 
 ; MIPS64-EL:     ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
+; MIPS64R2-EL:   ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
 ; MIPS64-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
+; MIPS64R2-EB:   ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
 
 ; MIPS64-EL-DAG:    lwl $[[R1:[0-9]+]], 3($[[PTR]])
 ; MIPS64-EL-DAG:    lwr $[[R1]], 0($[[PTR]])
 ; MIPS64-EL-DAG:    swl $[[R1]], 7($[[PTR]])
 ; MIPS64-EL-DAG:    swr $[[R1]], 4($[[PTR]])
 
+; MIPS64R2-EL-DAG:    lwl $[[R1:[0-9]+]], 3($[[PTR]])
+; MIPS64R2-EL-DAG:    lwr $[[R1]], 0($[[PTR]])
+; MIPS64R2-EL-DAG:    swl $[[R1]], 7($[[PTR]])
+; MIPS64R2-EL-DAG:    swr $[[R1]], 4($[[PTR]])
+
 ; MIPS64-EB-DAG:    lwl $[[R1:[0-9]+]], 0($[[PTR]])
 ; MIPS64-EB-DAG:    lwr $[[R1]], 3($[[PTR]])
 ; MIPS64-EB-DAG:    swl $[[R1]], 4($[[PTR]])
 ; MIPS64-EB-DAG:    swr $[[R1]], 7($[[PTR]])
 
+; MIPS64R2-EB-DAG:    lwl $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64R2-EB-DAG:    lwr $[[R1]], 3($[[PTR]])
+; MIPS64R2-EB-DAG:    swl $[[R1]], 4($[[PTR]])
+; MIPS64R2-EB-DAG:    swr $[[R1]], 7($[[PTR]])
 
 ; MIPS64-NOLEFTRIGHT-DAG:    lbu $[[R1:[0-9]+]], 0($[[PTR]])
 ; MIPS64-NOLEFTRIGHT-DAG:    sb $[[R1]], 4($[[PTR]])
@@ -365,12 +422,25 @@ entry:
 ; MIPS64-EL-DAG: sdl $[[R1]],       15($[[PTR]])
 ; MIPS64-EL-DAG: sdr $[[R1]],        8($[[PTR]])
 
+; MIPS64R2-EL:     ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
+
+; MIPS64R2-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]])
+; MIPS64R2-EL-DAG: ldr $[[R1]],        0($[[PTR]])
+; MIPS64R2-EL-DAG: sdl $[[R1]],       15($[[PTR]])
+; MIPS64R2-EL-DAG: sdr $[[R1]],        8($[[PTR]])
+
 ; MIPS64-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
 ; MIPS64-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]])
 ; MIPS64-EB-DAG: ldr $[[R1]],        7($[[PTR]])
 ; MIPS64-EB-DAG: sdl $[[R1]],        8($[[PTR]])
 ; MIPS64-EB-DAG: sdr $[[R1]],       15($[[PTR]])
 
+; MIPS64R2-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
+; MIPS64R2-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]])
+; MIPS64R2-EB-DAG: ldr $[[R1]],        7($[[PTR]])
+; MIPS64R2-EB-DAG: sdl $[[R1]],        8($[[PTR]])
+; MIPS64R2-EB-DAG: sdr $[[R1]],       15($[[PTR]])
+
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
 ; MIPS64R6-DAG:  ld $[[R1:[0-9]+]], 0($[[PTR]])
 ; MIPS64R6-DAG:  sd $[[R1]],        8($[[PTR]])
@@ -430,6 +500,10 @@ entry:
 ; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
 ; MIPS64-EL-DAG: lwr $[[R1]],   0($[[PTR]])
 
+; MIPS64R2-EL:     ld $[[SPTR:[0-9]+]], %got_disp(arr)(
+; MIPS64R2-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])
+; MIPS64R2-EL-DAG: lwr $[[R1]],   0($[[PTR]])
+
 ; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
 ; MIPS64-EB-DAG: lbu  $[[R2:[0-9]+]], 5($[[PTR]])
 ; MIPS64-EB-DAG: lbu  $[[R3:[0-9]+]], 4($[[PTR]])
@@ -444,6 +518,21 @@ entry:
 ; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8
 ; MIPS64-EB-DAG: or   $4, $[[T3]], $[[T4]]
 
+; MIPS64R2-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
+; MIPS64R2-EB-DAG: lbu  $[[R1:[0-9]+]], 5($[[PTR]])
+; MIPS64R2-EB-DAG: lbu  $[[R2:[0-9]+]], 4($[[PTR]])
+; MIPS64R2-EB-DAG: dsll $[[T0:[0-9]+]], $[[R2]], 8
+; MIPS64R2-EB-DAG: or   $[[T1:[0-9]+]], $[[T0]], $[[R1]]
+; MIPS64R2-EB-DAG: dsll $[[T1]], $[[T1]], 16
+; MIPS64R2-EB-DAG: lwl  $[[R3:[0-9]+]], 0($[[PTR]])
+; MIPS64R2-EB-DAG: lwr  $[[R3]], 3($[[PTR]])
+; MIPS64R2-EB-DAG: dext $[[R3]], $[[R3]], 0, 32
+; MIPS64R2-EB-DAG: dsll $[[R3]], $[[R3]], 32
+; MIPS64R2-EB-DAG: or   $[[T2:[0-9]+]], $[[R3]], $[[T1]]
+; MIPS64R2-EB-DAG: lbu  $[[R4:[0-9]+]], 6($[[PTR]])
+; MIPS64R2-EB-DAG: dsll $[[T3:[0-9]+]], $[[R4]], 8
+; MIPS64R2-EB-DAG: or   $4, $[[T2]], $[[T3]]
+
 ; MIPS64R6:      ld $[[SPTR:[0-9]+]], %got_disp(arr)(
 
   tail call void @extern_func([7 x i8]* byval @arr) nounwind