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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-12 04:58:45 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-12 04:58:45 +0000 |
| commit | ee5af50eb0c3b40bed784ba3f8bde1b06c0f6804 (patch) | |
| tree | 6f707085bd0b8dd64effb0e83a6155fe06774886 /llvm/test/CodeGen/Mips/llvm-ir | |
| parent | 27ed1c5bb80c8da317cd80bdd50cb22189d1c6fb (diff) | |
| download | bcm5719-llvm-ee5af50eb0c3b40bed784ba3f8bde1b06c0f6804.tar.gz bcm5719-llvm-ee5af50eb0c3b40bed784ba3f8bde1b06c0f6804.zip | |
[mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6
There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink
tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly
selects the `JALRC16` compact 2-byte instruction which takes a target
instruction address from a register only and assign `R_MIPS_32` relocation
for this instruction. This relocation completely overwrites `JALRC16`
and nearby instructions.
This patch adds missed matching patterns, selects `BALC` instruction and
assign a correct `R_MICROMIPS_PC26_S1` relocation.
Differential Revision: https://reviews.llvm.org/D64552
llvm-svn: 365870
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll index 6b4fd603056..3bf17abc796 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -208,7 +208,7 @@ define i32 @test1(float %t) { ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}> ; MMR6-SF-NEXT: # <MCOperand Imm:20>> ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6 +; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6 ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>> ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW @@ -399,7 +399,7 @@ define i32 @test2(double %t) { ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}> ; MMR6-SF-NEXT: # <MCOperand Imm:20>> ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6 +; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6 ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>> ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW |
