summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/Mips/llvm-ir
diff options
context:
space:
mode:
authorGeoff Berry <gberry@codeaurora.org>2018-02-01 18:54:01 +0000
committerGeoff Berry <gberry@codeaurora.org>2018-02-01 18:54:01 +0000
commit94503c7bc3d70f51ab03c03b2067db3e973efa19 (patch)
tree8db2d28d7793aa60b2cde1e630798f3e3c3fd6e7 /llvm/test/CodeGen/Mips/llvm-ir
parenta95bd9f72414a7d26f21a4ee5a0f40ff1d0c951a (diff)
downloadbcm5719-llvm-94503c7bc3d70f51ab03c03b2067db3e973efa19.tar.gz
bcm5719-llvm-94503c7bc3d70f51ab03c03b2067db3e973efa19.zip
[MachineCopyPropagation] Extend pass to do COPY source forwarding
Summary: This change extends MachineCopyPropagation to do COPY source forwarding and adds an additional run of the pass to the default pass pipeline just after register allocation. This version of this patch uses the newly added MachineOperand::isRenamable bit to avoid forwarding registers is such a way as to violate constraints that aren't captured in the Machine IR (e.g. ABI or ISA constraints). This change is a continuation of the work started in D30751. Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits Differential Revision: https://reviews.llvm.org/D41835 llvm-svn: 323991
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir')
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/ashr.ll4
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/lshr.ll12
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/shl.ll4
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/sub.ll2
4 files changed, 11 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index ec1e9b03b45..bc3a92550ff 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -800,7 +800,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: srlv $4, $8, $16
+; MMR3-NEXT: srlv $4, $7, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
@@ -890,7 +890,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: lw $3, 68($sp)
; MMR6-NEXT: li16 $2, 64
; MMR6-NEXT: subu16 $7, $2, $3
-; MMR6-NEXT: sllv $8, $6, $7
+; MMR6-NEXT: sllv $8, $5, $7
; MMR6-NEXT: andi16 $5, $7, 32
; MMR6-NEXT: selnez $9, $8, $5
; MMR6-NEXT: sllv $16, $4, $7
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index 057a7fb237e..8a6e6fccb28 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -828,7 +828,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: move $17, $5
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: srlv $7, $8, $16
+; MMR3-NEXT: srlv $7, $7, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
@@ -915,14 +915,14 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: move $1, $7
; MMR6-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MMR6-NEXT: move $16, $4
-; MMR6-NEXT: sw $16, 32($sp) # 4-byte Folded Spill
+; MMR6-NEXT: sw $4, 32($sp) # 4-byte Folded Spill
; MMR6-NEXT: lw $3, 76($sp)
-; MMR6-NEXT: srlv $2, $1, $3
+; MMR6-NEXT: srlv $2, $7, $3
; MMR6-NEXT: not16 $5, $3
; MMR6-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MMR6-NEXT: move $4, $6
-; MMR6-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
-; MMR6-NEXT: sll16 $6, $4, 1
+; MMR6-NEXT: sw $6, 28($sp) # 4-byte Folded Spill
+; MMR6-NEXT: sll16 $6, $6, 1
; MMR6-NEXT: sllv $17, $6, $5
; MMR6-NEXT: or16 $17, $2
; MMR6-NEXT: addiu $7, $3, -64
@@ -956,7 +956,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $6, $6
; MMR6-NEXT: move $7, $17
-; MMR6-NEXT: srl16 $17, $7, 1
+; MMR6-NEXT: srl16 $17, $17, 1
; MMR6-NEXT: srlv $6, $17, $6
; MMR6-NEXT: lw $17, 4($sp) # 4-byte Folded Reload
; MMR6-NEXT: or16 $6, $17
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
index 6c764b8ad43..247e2b8943f 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -857,7 +857,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: sw $5, 32($sp) # 4-byte Folded Spill
; MMR3-NEXT: move $1, $4
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: sllv $2, $1, $16
+; MMR3-NEXT: sllv $2, $4, $16
; MMR3-NEXT: not16 $4, $16
; MMR3-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: srl16 $3, $5, 1
@@ -946,7 +946,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: move $1, $4
; MMR6-NEXT: lw $3, 60($sp)
-; MMR6-NEXT: sllv $2, $1, $3
+; MMR6-NEXT: sllv $2, $4, $3
; MMR6-NEXT: not16 $4, $3
; MMR6-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
index d06170f1db1..d839a6e4c88 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -163,7 +163,7 @@ entry:
; MMR3: subu16 $5, $[[T19]], $[[T20]]
; MMR6: move $[[T0:[0-9]+]], $7
-; MMR6: sw $[[T0]], 8($sp)
+; MMR6: sw $7, 8($sp)
; MMR6: move $[[T1:[0-9]+]], $5
; MMR6: sw $4, 12($sp)
; MMR6: lw $[[T2:[0-9]+]], 48($sp)
OpenPOWER on IntegriCloud