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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-13 11:07:53 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-13 11:08:12 +0000 |
| commit | 8f49204f26ea8856b870d4c2344b98f4b706bea0 (patch) | |
| tree | 70fb38f062d77cd099787b5d02a25f7e5fb1b920 /llvm/test/CodeGen/Mips/llvm-ir | |
| parent | 7f1cf7d5f658b15abb8bd6840fc01e6d44487a23 (diff) | |
| download | bcm5719-llvm-8f49204f26ea8856b870d4c2344b98f4b706bea0.tar.gz bcm5719-llvm-8f49204f26ea8856b870d4c2344b98f4b706bea0.zip | |
[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)
As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.
This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits.
Differential Revision: https://reviews.llvm.org/D72573
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 62 |
1 files changed, 20 insertions, 42 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll index b3efdcca4ad..ed2bfc9fcf6 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -94,68 +94,57 @@ entry: define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { ; MIPS2-LABEL: lshr_i8: ; MIPS2: # %bb.0: # %entry -; MIPS2-NEXT: srlv $1, $4, $5 ; MIPS2-NEXT: jr $ra -; MIPS2-NEXT: andi $2, $1, 255 +; MIPS2-NEXT: srlv $2, $4, $5 ; ; MIPS32-LABEL: lshr_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: srlv $1, $4, $5 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: andi $2, $1, 255 +; MIPS32-NEXT: srlv $2, $4, $5 ; ; MIPS32R2-LABEL: lshr_i8: ; MIPS32R2: # %bb.0: # %entry -; MIPS32R2-NEXT: srlv $1, $4, $5 ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: andi $2, $1, 255 +; MIPS32R2-NEXT: srlv $2, $4, $5 ; ; MIPS32R6-LABEL: lshr_i8: ; MIPS32R6: # %bb.0: # %entry -; MIPS32R6-NEXT: srlv $1, $4, $5 ; MIPS32R6-NEXT: jr $ra -; MIPS32R6-NEXT: andi $2, $1, 255 +; MIPS32R6-NEXT: srlv $2, $4, $5 ; ; MIPS3-LABEL: lshr_i8: ; MIPS3: # %bb.0: # %entry -; MIPS3-NEXT: srlv $1, $4, $5 ; MIPS3-NEXT: jr $ra -; MIPS3-NEXT: andi $2, $1, 255 +; MIPS3-NEXT: srlv $2, $4, $5 ; ; MIPS4-LABEL: lshr_i8: ; MIPS4: # %bb.0: # %entry -; MIPS4-NEXT: srlv $1, $4, $5 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: andi $2, $1, 255 +; MIPS4-NEXT: srlv $2, $4, $5 ; ; MIPS64-LABEL: lshr_i8: ; MIPS64: # %bb.0: # %entry -; MIPS64-NEXT: srlv $1, $4, $5 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: andi $2, $1, 255 +; MIPS64-NEXT: srlv $2, $4, $5 ; ; MIPS64R2-LABEL: lshr_i8: ; MIPS64R2: # %bb.0: # %entry -; MIPS64R2-NEXT: srlv $1, $4, $5 ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: andi $2, $1, 255 +; MIPS64R2-NEXT: srlv $2, $4, $5 ; ; MIPS64R6-LABEL: lshr_i8: ; MIPS64R6: # %bb.0: # %entry -; MIPS64R6-NEXT: srlv $1, $4, $5 ; MIPS64R6-NEXT: jr $ra -; MIPS64R6-NEXT: andi $2, $1, 255 +; MIPS64R6-NEXT: srlv $2, $4, $5 ; ; MMR3-LABEL: lshr_i8: ; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra ; MMR3-NEXT: srlv $2, $4, $5 -; MMR3-NEXT: andi16 $2, $2, 255 -; MMR3-NEXT: jrc $ra ; ; MMR6-LABEL: lshr_i8: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: srlv $2, $4, $5 -; MMR6-NEXT: andi16 $2, $2, 255 ; MMR6-NEXT: jrc $ra entry: @@ -166,68 +155,57 @@ entry: define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { ; MIPS2-LABEL: lshr_i16: ; MIPS2: # %bb.0: # %entry -; MIPS2-NEXT: srlv $1, $4, $5 ; MIPS2-NEXT: jr $ra -; MIPS2-NEXT: andi $2, $1, 65535 +; MIPS2-NEXT: srlv $2, $4, $5 ; ; MIPS32-LABEL: lshr_i16: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: srlv $1, $4, $5 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: andi $2, $1, 65535 +; MIPS32-NEXT: srlv $2, $4, $5 ; ; MIPS32R2-LABEL: lshr_i16: ; MIPS32R2: # %bb.0: # %entry -; MIPS32R2-NEXT: srlv $1, $4, $5 ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: andi $2, $1, 65535 +; MIPS32R2-NEXT: srlv $2, $4, $5 ; ; MIPS32R6-LABEL: lshr_i16: ; MIPS32R6: # %bb.0: # %entry -; MIPS32R6-NEXT: srlv $1, $4, $5 ; MIPS32R6-NEXT: jr $ra -; MIPS32R6-NEXT: andi $2, $1, 65535 +; MIPS32R6-NEXT: srlv $2, $4, $5 ; ; MIPS3-LABEL: lshr_i16: ; MIPS3: # %bb.0: # %entry -; MIPS3-NEXT: srlv $1, $4, $5 ; MIPS3-NEXT: jr $ra -; MIPS3-NEXT: andi $2, $1, 65535 +; MIPS3-NEXT: srlv $2, $4, $5 ; ; MIPS4-LABEL: lshr_i16: ; MIPS4: # %bb.0: # %entry -; MIPS4-NEXT: srlv $1, $4, $5 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: andi $2, $1, 65535 +; MIPS4-NEXT: srlv $2, $4, $5 ; ; MIPS64-LABEL: lshr_i16: ; MIPS64: # %bb.0: # %entry -; MIPS64-NEXT: srlv $1, $4, $5 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: andi $2, $1, 65535 +; MIPS64-NEXT: srlv $2, $4, $5 ; ; MIPS64R2-LABEL: lshr_i16: ; MIPS64R2: # %bb.0: # %entry -; MIPS64R2-NEXT: srlv $1, $4, $5 ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: andi $2, $1, 65535 +; MIPS64R2-NEXT: srlv $2, $4, $5 ; ; MIPS64R6-LABEL: lshr_i16: ; MIPS64R6: # %bb.0: # %entry -; MIPS64R6-NEXT: srlv $1, $4, $5 ; MIPS64R6-NEXT: jr $ra -; MIPS64R6-NEXT: andi $2, $1, 65535 +; MIPS64R6-NEXT: srlv $2, $4, $5 ; ; MMR3-LABEL: lshr_i16: ; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra ; MMR3-NEXT: srlv $2, $4, $5 -; MMR3-NEXT: andi16 $2, $2, 65535 -; MMR3-NEXT: jrc $ra ; ; MMR6-LABEL: lshr_i16: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: srlv $2, $4, $5 -; MMR6-NEXT: andi16 $2, $2, 65535 ; MMR6-NEXT: jrc $ra entry: |
