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| author | Aleksandar Beserminji <Aleksandar.Beserminji@imgtec.com> | 2017-09-29 11:05:02 +0000 |
|---|---|---|
| committer | Aleksandar Beserminji <Aleksandar.Beserminji@imgtec.com> | 2017-09-29 11:05:02 +0000 |
| commit | 29341b88ac25ad8320f7d3522a66d175898d555f (patch) | |
| tree | 66618ed5128e0024e6e8e343ef15802fb815226e /llvm/test/CodeGen/Mips/llvm-ir | |
| parent | a0a01e7172ecc7bb00da42013254fde760a45f59 (diff) | |
| download | bcm5719-llvm-29341b88ac25ad8320f7d3522a66d175898d555f.tar.gz bcm5719-llvm-29341b88ac25ad8320f7d3522a66d175898d555f.zip | |
[mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.
Recommitting r314497. This version does not contain test which fails
when compiler is not build in debug mode.
Differential Revision: https://reviews.llvm.org/D37328
llvm-svn: 314507
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/mul.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/srem.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/udiv.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/urem.ll | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll index 1562372ce9a..e32aa646c04 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll @@ -268,7 +268,7 @@ entry: ; MM64R6: daddu $2, $[[T1]], $[[T0]] ; MM64R6-DAG: dmul $3, $5, $7 - ; MM32: lw $25, %call16(__multi3)($16) + ; MM32: lw $25, %call16(__multi3) %r = mul i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll index defd25bb41a..087b28b3acd 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -190,7 +190,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) ; 64R6: ld $25, %call16(__divti3)($gp) - ; MM32: lw $25, %call16(__divti3)($16) + ; MM32: lw $25, %call16(__divti3) ; MM64: ld $25, %call16(__divti3)($2) diff --git a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll index 42664d7457e..7466e5679bb 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll @@ -182,7 +182,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) ; 64R6: ld $25, %call16(__modti3)($gp) - ; MM32: lw $25, %call16(__modti3)($16) + ; MM32: lw $25, %call16(__modti3) ; MM64: ld $25, %call16(__modti3)($2) diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll index 78ab36442a9..122d1385353 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -152,7 +152,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) ; 64-R6: ld $25, %call16(__udivti3)($gp) - ; MM32: lw $25, %call16(__udivti3)($16) + ; MM32: lw $25, %call16(__udivti3) ; MM64: ld $25, %call16(__udivti3)($2) diff --git a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll index 160c126c7e3..7fd3d79f843 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll @@ -208,7 +208,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) ; 64R6: ld $25, %call16(__umodti3)($gp) - ; MM32: lw $25, %call16(__umodti3)($16) + ; MM32: lw $25, %call16(__umodti3) ; MM64: ld $25, %call16(__umodti3)($2) |
