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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-02-18 16:24:50 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-02-18 16:24:50 +0000 |
| commit | 1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e (patch) | |
| tree | eb72a1ebc9ba0e8d0408b76b86874f22dc31dc81 /llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll | |
| parent | 298beb5e86f6d92638ccb1c5213c59ebd7e45781 (diff) | |
| download | bcm5719-llvm-1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e.tar.gz bcm5719-llvm-1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e.zip | |
[mips] Add backend support for Mips32r[35] and Mips64r[35].
Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: tomatabacu, llvm-commits, atanasyan
Differential Revision: http://reviews.llvm.org/D7381
llvm-svn: 229695
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll index 54b7f70b1da..929ee88bb7f 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -3,7 +3,11 @@ ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32 +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefix=R6 -check-prefix=GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ @@ -13,7 +17,11 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6 +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=R6 -check-prefix=64R6 @@ -49,11 +57,11 @@ entry: ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 ; NOT-R2-R6: sra $2, $[[T1]], 24 - ; R2: div $zero, $4, $5 - ; R2: teq $5, $zero, 7 - ; R2: mflo $[[T0:[0-9]+]] + ; R2-R5: div $zero, $4, $5 + ; R2-R5: teq $5, $zero, 7 + ; R2-R5: mflo $[[T0:[0-9]+]] ; FIXME: This instruction is redundant. - ; R2: seb $2, $[[T0]] + ; R2-R5: seb $2, $[[T0]] ; R6: div $[[T0:[0-9]+]], $4, $5 ; R6: teq $5, $zero, 7 @@ -75,11 +83,11 @@ entry: ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 ; NOT-R2-R6: sra $2, $[[T1]], 16 - ; R2: div $zero, $4, $5 - ; R2: teq $5, $zero, 7 - ; R2: mflo $[[T0:[0-9]+]] + ; R2-R5: div $zero, $4, $5 + ; R2-R5: teq $5, $zero, 7 + ; R2-R5: mflo $[[T0:[0-9]+]] ; FIXME: This is instruction is redundant since div is signed. - ; R2: seh $2, $[[T0]] + ; R2-R5: seh $2, $[[T0]] ; R6: div $[[T0:[0-9]+]], $4, $5 ; R6: teq $5, $zero, 7 |
