diff options
| author | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-01-26 12:33:22 +0000 |
|---|---|---|
| committer | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2015-01-26 12:33:22 +0000 |
| commit | ef96a8ecd6308cc31e43515c2ce0bae6ffbdbbc6 (patch) | |
| tree | 8690f9c5f08e73ef25a3bc3d7e4ec148cb077997 /llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | |
| parent | dceac987bd219730f99b477f7d730486ad39d683 (diff) | |
| download | bcm5719-llvm-ef96a8ecd6308cc31e43515c2ce0bae6ffbdbbc6.tar.gz bcm5719-llvm-ef96a8ecd6308cc31e43515c2ce0bae6ffbdbbc6.zip | |
[mips] Enable arithmetic and binary operations for the i128 data type.
Summary:
This patch adds support for some operations that were missing from
128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these
changes we can support the __int128_t and __uint128_t data types
from C/C++.
Depends on D7125
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7143
llvm-svn: 227089
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir/lshr.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll index 8975c8cccdf..1679678d5d7 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -119,3 +119,58 @@ entry: %r = lshr i64 %a, %b ret i64 %r } + +define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: lshr_i128: + + ; GP32: lw $25, %call16(__lshrti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $3, $[[T1]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsll $[[T5:[0-9]+]], $4, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $3, $[[T7]], $[[T4]] + ; M3: $[[BB0]]: + ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: move $2, $[[T1]] + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] + ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 + ; GP64-NOT-R6: movn $3, $2, $[[T5]] + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $2, $zero, $1 + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; 64R6: dsll $[[T2:[0-9]+]], $4, 1 + ; 64R6: not $[[T3:[0-9]+]], $[[T0]] + ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 + ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 + ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] + ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]] + ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] + ; 64R6: or $3, $[[T10]], $[[T8]] + ; 64R6: jr $ra + ; 64R6: seleqz $2, $[[T0]], $[[T7]] + + %r = lshr i128 %a, %b + ret i128 %r +} |
