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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-02-18 16:24:50 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-02-18 16:24:50 +0000 |
| commit | 1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e (patch) | |
| tree | eb72a1ebc9ba0e8d0408b76b86874f22dc31dc81 /llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | |
| parent | 298beb5e86f6d92638ccb1c5213c59ebd7e45781 (diff) | |
| download | bcm5719-llvm-1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e.tar.gz bcm5719-llvm-1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e.zip | |
[mips] Add backend support for Mips32r[35] and Mips64r[35].
Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: tomatabacu, llvm-commits, atanasyan
Differential Revision: http://reviews.llvm.org/D7381
llvm-svn: 229695
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir/lshr.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll index 9336f0a5349..7344d950cad 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -3,10 +3,16 @@ ; RUN: -check-prefix=M2 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R2 +; RUN: -check-prefix=32R1-R5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R2 +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP32 \ ; RUN: -check-prefix=32R6 @@ -22,6 +28,12 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 \ ; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 \ ; RUN: -check-prefix=64R6 @@ -89,16 +101,16 @@ entry: ; M2: jr $ra ; M2: nop - ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R1-R2: not $[[T1:[0-9]+]], $7 - ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1 - ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R2: or $3, $[[T3]], $[[T0]] - ; 32R1-R2: srlv $[[T4:[0-9]+]], $4, $7 - ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R2: movn $3, $[[T4]], $[[T5]] - ; 32R1-R2: jr $ra - ; 32R1-R2: movn $2, $zero, $[[T5]] + ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R1-R5: not $[[T1:[0-9]+]], $7 + ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 + ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R5: or $3, $[[T3]], $[[T0]] + ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7 + ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R5: movn $3, $[[T4]], $[[T5]] + ; 32R1-R5: jr $ra + ; 32R1-R5: movn $2, $zero, $[[T5]] ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 ; 32R6: not $[[T1:[0-9]+]], $7 |
