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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-11-16 14:14:59 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-11-16 14:14:59 +0000 |
| commit | 00a4aaceccdf0d686423d6b5ea09b6c172979d7a (patch) | |
| tree | 5587399e0e6ea9ae5cd6f6a505f539c9794aec1c /llvm/test/CodeGen/Mips/inlineasm_constraint.ll | |
| parent | afb3cb154bd305defae28f332d33acb2cdc1cd4b (diff) | |
| download | bcm5719-llvm-00a4aaceccdf0d686423d6b5ea09b6c172979d7a.tar.gz bcm5719-llvm-00a4aaceccdf0d686423d6b5ea09b6c172979d7a.zip | |
[mips][ias] Allow whitespace after commas in inlineasm*.ll tests.
IAS always prints whitespace after a comma. NFC at the moment but this will
prevent failures when IAS is enabled.
llvm-svn: 253208
Diffstat (limited to 'llvm/test/CodeGen/Mips/inlineasm_constraint.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm_constraint.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/Mips/inlineasm_constraint.ll b/llvm/test/CodeGen/Mips/inlineasm_constraint.ll index 868433e0941..145821ea4c9 100644 --- a/llvm/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/llvm/test/CodeGen/Mips/inlineasm_constraint.ll @@ -5,51 +5,51 @@ entry: ; First I with short ; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096 ; CHECK: #NO_APP - tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind + tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind ; Then I with int ; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind ; Now J with 0 ; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind + tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind ; Now K with 64 ; CHECK: #APP -; CHECK: addu ${{[0-9]+}},${{[0-9]+}},64 +; CHECK: addu ${{[0-9]+}}, ${{[0-9]+}}, 64 ; CHECK: #NO_APP - tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind + tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind ; Now L with 0x00100000 ; CHECK: #APP -; CHECK: add ${{[0-9]+}},${{[0-9]+}},${{[0-9]+}} +; CHECK: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; CHECK: #NO_APP - tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind + tail call i32 asm sideeffect "add $0, $1, $3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind ; Now N with -3 ; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,N"(i32 7, i32 -3) nounwind ; Now O with -3 ; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,O"(i32 7, i16 -3) nounwind ; Now P with 65535 ; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},65535 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535 ; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,P"(i32 7, i32 65535) nounwind ret i32 0 } |
