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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-22 11:46:58 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-22 11:46:58 +0000 |
| commit | b230595839918e57b0a887d2a4ec1c6fc3d7de8a (patch) | |
| tree | a7f3a3ed94645fe47ccefb72f43d1ff94f016a01 /llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll | |
| parent | 9288b2181f1d89b90df0496a1f4bba0bb16d99ce (diff) | |
| download | bcm5719-llvm-b230595839918e57b0a887d2a4ec1c6fc3d7de8a.tar.gz bcm5719-llvm-b230595839918e57b0a887d2a4ec1c6fc3d7de8a.zip | |
[mips] Use addiu in inline assembly tests since addi is not available in all ISA's
Summary:
This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when
-integrated-as is enabled by default and we correctly detect the host CPU.
No functional change since these tests are testing the behaviour of the
constraint used for the third operand rather than the mnemonic.
Depends on D3842
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3843
llvm-svn: 209421
Diffstat (limited to 'llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll index 78706660257..a7ba762b106 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll @@ -12,9 +12,9 @@ entry: ; r with long long ;CHECK: #APP -;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3 ;CHECK: #NO_APP - tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind + tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind ret i32 0 } |
