Revert "[mips] Promote the result of SETCC nodes to GPR width."

This reverts commit r262316.

It seems that my change breaks an out-of-tree chromium buildbot, so
I'm reverting this in order to investigate the situation further.

llvm-svn: 262387

1 files changed, 58 insertions, 116 deletions

diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index 4613f698bd0..aa1f09bf7ab 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -29,21 +29,17 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
-; FIXME: The sign extension below is redundant.
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    dmfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    sll $[[T2:[0-9]+]], $[[T1]], 0
-; 64-CMP-DAG:    andi $2, $[[T2]], 1
+; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
@@ -57,11 +53,9 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -83,11 +77,9 @@ define i32 @oge_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -109,11 +101,9 @@ define i32 @olt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -135,11 +125,9 @@ define i32 @ole_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -161,11 +149,9 @@ define i32 @one_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -189,11 +175,9 @@ define i32 @ord_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -217,11 +201,9 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -243,11 +225,9 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -269,11 +249,9 @@ define i32 @uge_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -295,11 +273,9 @@ define i32 @ult_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -322,11 +298,9 @@ define i32 @ule_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -348,11 +322,9 @@ define i32 @une_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -376,11 +348,9 @@ define i32 @uno_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -420,11 +390,9 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -446,11 +414,9 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -472,11 +438,9 @@ define i32 @oge_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -498,11 +462,9 @@ define i32 @olt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -524,11 +486,9 @@ define i32 @ole_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -550,11 +510,9 @@ define i32 @one_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -578,11 +536,9 @@ define i32 @ord_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -606,11 +562,9 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -632,11 +586,9 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -658,11 +610,9 @@ define i32 @uge_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -684,11 +634,9 @@ define i32 @ult_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -710,11 +658,9 @@ define i32 @ule_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -736,11 +682,9 @@ define i32 @une_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -764,11 +708,9 @@ define i32 @uno_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      addiu $2, $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]