[mips] Teach the delay slot filler to remove needless KILL instructions.

Summary:
Previously, the presence of KILL instructions would block valid candidates
from filling a specific delay slot. With the elimination of the KILL
instructions, in the appropriate range, we are able to fill more slots and
keep the information from future def/use analysis consistent.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D7724

llvm-svn: 235183

1 files changed, 14 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/delay-slot-kill.ll b/llvm/test/CodeGen/Mips/delay-slot-kill.ll
new file mode 100644
index 00000000000..57b630303c2
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/delay-slot-kill.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
+
+; Currently, the following IR assembly generates a KILL instruction between
+; the bitwise-and instruction and the return instruction. We verify that the
+; delay slot filler ignores such KILL instructions by filling the slot of the
+; return instruction properly.
+define signext i32 @f1(i32 signext %a, i32 signext %b) {
+entry:
+  ; CHECK:          jr      $ra
+  ; CHECK-NEXT:     and     $2, $4, $5
+
+  %r = and i32 %a, %b
+  ret i32 %r
+}