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| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-07-11 07:41:56 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-07-11 07:41:56 +0000 |
| commit | cba9f80ba87610b5f46f1baccbad548f2f15f0c6 (patch) | |
| tree | 411fa795b35aae5c553f76318cae14e0cde3c0a0 /llvm/test/CodeGen/Mips/cconv | |
| parent | 4d61a3c2d8864bec52e4d2ca700cbbbc10e5797f (diff) | |
| download | bcm5719-llvm-cba9f80ba87610b5f46f1baccbad548f2f15f0c6.tar.gz bcm5719-llvm-cba9f80ba87610b5f46f1baccbad548f2f15f0c6.zip | |
[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D18824
llvm-svn: 275050
Diffstat (limited to 'llvm/test/CodeGen/Mips/cconv')
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll index 9b503fc938e..30a5727f344 100644 --- a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll +++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll @@ -18,6 +18,8 @@ ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s + ; Test the the callee-saved registers are callee-saved as specified by section ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. @@ -109,3 +111,6 @@ entry: ; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp) ; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp) ; N64: addiu $sp, $sp, 64 + +; Check the mapping between LDC164 and LDC1_64_MMR6. +; MM32R6: ldc1 |
