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authorReed Kotler <rkotler@mips.com>2014-09-15 20:30:25 +0000
committerReed Kotler <rkotler@mips.com>2014-09-15 20:30:25 +0000
commit32be74b17828ae823ece24b967eae5a9b6a7aaed (patch)
tree26808fc1ff563f2dcf34c01fa2b1992bbeac6c46 /llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
parent15f7ed96ac71c7a53b8f1ea667914775a3af51b1 (diff)
downloadbcm5719-llvm-32be74b17828ae823ece24b967eae5a9b6a7aaed.tar.gz
bcm5719-llvm-32be74b17828ae823ece24b967eae5a9b6a7aaed.zip
Add mips32 r1 to the list of supported targets for Mips fast-isel
Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 llvm-svn: 217821
Diffstat (limited to 'llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll')
-rw-r--r--llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
index f113a0eb1d5..d84478b9c5a 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
@@ -6,6 +6,8 @@ target triple = "mips--linux-gnu"
@c1 = common global i8 0, align 1
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
@s2 = common global i16 0, align 2
@s1 = common global i16 0, align 2
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