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| author | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2016-10-18 13:05:42 +0000 |
|---|---|---|
| committer | Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> | 2016-10-18 13:05:42 +0000 |
| commit | 3955b75ba9c2f5888d2e3113ebf9d72d97f047eb (patch) | |
| tree | 301800fc1bbdbbfd4d8ae65eae09ad59d691d4b3 /llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll | |
| parent | 9f578ceed72734025803c54c30aae4c3669fbb9e (diff) | |
| download | bcm5719-llvm-3955b75ba9c2f5888d2e3113ebf9d72d97f047eb.tar.gz bcm5719-llvm-3955b75ba9c2f5888d2e3113ebf9d72d97f047eb.zip | |
[mips][FastISel] Instantiate the MipsFastISel class only for targets that support FastISel.
Summary:
Instead of instantiating the MipsFastISel class and checking if the
target is supported in the overriden methods, we should perform that
check before creating the class. This allows us to enable FastISel *only*
for targets that truly support it, ie. MIPS32 to MIPS32R5.
Reviewers: sdardis
Subscribers: ehostunreach, llvm-commits
Differential Revision: https://reviews.llvm.org/D24824
llvm-svn: 284475
Diffstat (limited to 'llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll index ee77d43d2b0..eb592189e60 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll @@ -1,5 +1,5 @@ -; RUN: not llc -march=mipsel -mcpu=mips32r2 -fast-isel -mattr=+fp64 < %s \ -; RUN: -fast-isel-abort=3 +; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ +; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s ; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently ; supports AFGR64 only, which uses paired 32 bit registers. |
