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| author | Nirav Dave <niravd@google.com> | 2017-07-05 01:21:23 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-07-05 01:21:23 +0000 |
| commit | b320ef9fab604326507e011bf04aab17dd84a7d6 (patch) | |
| tree | 79145b50e488de598ede9e15616f45ec4184bbfe /llvm/test/CodeGen/MSP430 | |
| parent | ed37df7ea3ec2abbface106f888e7c7d27a93261 (diff) | |
| download | bcm5719-llvm-b320ef9fab604326507e011bf04aab17dd84a7d6.tar.gz bcm5719-llvm-b320ef9fab604326507e011bf04aab17dd84a7d6.zip | |
Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset
Relanding after rewriting undef.ll test to avoid host-dependant
endianness.
As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.
Tests of note:
* test/CodeGen/X86/build-vector* - Improved.
* test/CodeGen/BPF/undef.ll - Improved store alignment allows an
additional store merge
* test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
case we already do not handle well. Here, the DAG is improved, but
scheduling causes a code size degradation.
Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab
Subscribers: nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D34472
llvm-svn: 307114
Diffstat (limited to 'llvm/test/CodeGen/MSP430')
| -rw-r--r-- | llvm/test/CodeGen/MSP430/Inst16mm.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/MSP430/Inst16mm.ll b/llvm/test/CodeGen/MSP430/Inst16mm.ll index 951002d60a0..14a799b9171 100644 --- a/llvm/test/CodeGen/MSP430/Inst16mm.ll +++ b/llvm/test/CodeGen/MSP430/Inst16mm.ll @@ -64,6 +64,6 @@ entry: %0 = load i16, i16* %retval ; <i16> [#uses=1] ret i16 %0 ; CHECK-LABEL: mov2: -; CHECK: mov.w 0(r1), 4(r1) -; CHECK: mov.w 2(r1), 6(r1) +; CHECK-DAG: mov.w 2(r1), 6(r1) +; CHECK-DAG: mov.w 0(r1), 4(r1) } |
