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| author | Sanjay Patel <spatel@rotateright.com> | 2019-10-19 16:57:02 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-10-19 16:57:02 +0000 |
| commit | a298964d22a203d21bafe1f649a46ba8a2592ca4 (patch) | |
| tree | eb23601f4b9a654c2f39bbc195248a2dbac047f4 /llvm/test/CodeGen/MSP430 | |
| parent | 7d8ea71677f6b9985d4bbe5112067d5d48414383 (diff) | |
| download | bcm5719-llvm-a298964d22a203d21bafe1f649a46ba8a2592ca4.tar.gz bcm5719-llvm-a298964d22a203d21bafe1f649a46ba8a2592ca4.zip | |
[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)
Provides a TLI hook to allow targets to relax the emission of shifts, thus enabling
codegen improvements on targets with no multiple shift instructions and cheap selects
or branches.
Contributes to a Fix for PR43559:
https://bugs.llvm.org/show_bug.cgi?id=43559
Patch by: @joanlluch (Joan LLuch)
Differential Revision: https://reviews.llvm.org/D69116
llvm-svn: 375347
Diffstat (limited to 'llvm/test/CodeGen/MSP430')
| -rw-r--r-- | llvm/test/CodeGen/MSP430/shift-amount-threshold.ll | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll index a9c25a44533..633cd785dc1 100644 --- a/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll +++ b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll @@ -4,13 +4,9 @@ define i16 @testSimplifySetCC_0(i16 %a) { ; CHECK-LABEL: testSimplifySetCC_0: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: and #32, r12 -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 +; CHECK-NEXT: bit #32, r12 +; CHECK-NEXT: mov r2, r12 +; CHECK-NEXT: and #1, r12 ; CHECK-NEXT: ret entry: %and = and i16 %a, 32 @@ -22,13 +18,9 @@ entry: define i16 @testSimplifySetCC_1(i16 %a) { ; CHECK-LABEL: testSimplifySetCC_1: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: and #32, r12 -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 +; CHECK-NEXT: bit #32, r12 +; CHECK-NEXT: mov r2, r12 +; CHECK-NEXT: and #1, r12 ; CHECK-NEXT: ret entry: %and = and i16 %a, 32 |
