[MSP430] Add MC layer

Reapply r346374 with the fixes for modules build.

Original summary:

This change implements assembler parser, code emitter, ELF object writer
and disassembler for the MSP430 ISA.  Also, more instruction forms are added
to the target description.

Patch by Michael Skvortsov!

llvm-svn: 346948

30 files changed, 217 insertions, 217 deletions

diff --git a/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
index f4cb30f2d01..948b67eb66c 100644
--- a/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
+++ b/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -8,7 +8,7 @@ define i16 @am1(i16 %x, i16* %a) nounwind {
 	ret i16 %2
 }
 ; CHECK-LABEL: am1:
-; CHECK:		bis.w	0(r13), r12
+; CHECK:		bis	0(r13), r12
 
 @foo = external global i16
 
@@ -18,7 +18,7 @@ define i16 @am2(i16 %x) nounwind {
 	ret i16 %2
 }
 ; CHECK-LABEL: am2:
-; CHECK:		bis.w	&foo, r12
+; CHECK:		bis	&foo, r12
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
@@ -37,7 +37,7 @@ define i16 @am4(i16 %x) nounwind {
 	ret i16 %2
 }
 ; CHECK-LABEL: am4:
-; CHECK:		bis.w	&32, r12
+; CHECK:		bis	&32, r12
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
 	%1 = getelementptr i16, i16* %a, i16 2
@@ -46,7 +46,7 @@ define i16 @am5(i16 %x, i16* %a) nounwind {
 	ret i16 %3
 }
 ; CHECK-LABEL: am5:
-; CHECK:		bis.w	4(r13), r12
+; CHECK:		bis	4(r13), r12
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
@@ -57,7 +57,7 @@ define i16 @am6(i16 %x) nounwind {
 	ret i16 %2
 }
 ; CHECK-LABEL: am6:
-; CHECK:		bis.w	&baz+2, r12
+; CHECK:		bis	&baz+2, r12
 
 %T = type { i16, [2 x i8] }
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
diff --git a/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
index 1e150f38206..6d3a497386d 100644
--- a/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
+++ b/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
@@ -9,7 +9,7 @@ define void @am1(i16* %a, i16 %x) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am1:
-; CHECK:		bis.w	r13, 0(r12)
+; CHECK:		bis	r13, 0(r12)
 
 @foo = external global i16
 
@@ -20,7 +20,7 @@ define void @am2(i16 %x) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am2:
-; CHECK:		bis.w	r12, &foo
+; CHECK:		bis	r12, &foo
 
 @bar = external global [2 x i8]
 
@@ -41,7 +41,7 @@ define void @am4(i16 %x) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am4:
-; CHECK:		bis.w	r12, &32
+; CHECK:		bis	r12, &32
 
 define void @am5(i16* %a, i16 %x) readonly {
 	%1 = getelementptr inbounds i16, i16* %a, i16 2
@@ -51,7 +51,7 @@ define void @am5(i16* %a, i16 %x) readonly {
 	ret void
 }
 ; CHECK-LABEL: am5:
-; CHECK:		bis.w	r13, 4(r12)
+; CHECK:		bis	r13, 4(r12)
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer
@@ -63,7 +63,7 @@ define void @am6(i16 %x) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am6:
-; CHECK:		bis.w	r12, &baz+2
+; CHECK:		bis	r12, &baz+2
 
 %T = type { i16, [2 x i8] }
 @duh = external global %T
diff --git a/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
index 808aca0ea10..0605e8e86ce 100644
--- a/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
+++ b/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
@@ -7,7 +7,7 @@ define i16 @am1(i16* %a) nounwind {
 	ret i16 %1
 }
 ; CHECK-LABEL: am1:
-; CHECK:		mov.w	0(r12), r12
+; CHECK:		mov	0(r12), r12
 
 @foo = external global i16
 
@@ -16,7 +16,7 @@ define i16 @am2() nounwind {
 	ret i16 %1
 }
 ; CHECK-LABEL: am2:
-; CHECK:		mov.w	&foo, r12
+; CHECK:		mov	&foo, r12
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
 
@@ -33,7 +33,7 @@ define i16 @am4() nounwind {
 	ret i16 %1
 }
 ; CHECK-LABEL: am4:
-; CHECK:		mov.w	&32, r12
+; CHECK:		mov	&32, r12
 
 define i16 @am5(i16* %a) nounwind {
 	%1 = getelementptr i16, i16* %a, i16 2
@@ -41,7 +41,7 @@ define i16 @am5(i16* %a) nounwind {
 	ret i16 %2
 }
 ; CHECK-LABEL: am5:
-; CHECK:		mov.w	4(r12), r12
+; CHECK:		mov	4(r12), r12
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
@@ -51,7 +51,7 @@ define i16 @am6() nounwind {
 	ret i16 %1
 }
 ; CHECK-LABEL: am6:
-; CHECK:		mov.w	&baz+2, r12
+; CHECK:		mov	&baz+2, r12
 
 %T = type { i16, [2 x i8] }
 @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
diff --git a/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
index c336289a60d..acc0b825711 100644
--- a/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
+++ b/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -7,7 +7,7 @@ define void @am1(i16* %a, i16 %b) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am1:
-; CHECK:		mov.w	r13, 0(r12)
+; CHECK:		mov	r13, 0(r12)
 
 @foo = external global i16
 
@@ -16,7 +16,7 @@ define void @am2(i16 %a) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am2:
-; CHECK:		mov.w	r12, &foo
+; CHECK:		mov	r12, &foo
 
 @bar = external global [2 x i8]
 
@@ -33,7 +33,7 @@ define void @am4(i16 %a) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am4:
-; CHECK:		mov.w	r12, &32
+; CHECK:		mov	r12, &32
 
 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
 	%1 = getelementptr inbounds i16, i16* %p, i16 2
@@ -41,7 +41,7 @@ define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
 	ret void
 }
 ; CHECK-LABEL: am5:
-; CHECK:		mov.w	r13, 4(r12)
+; CHECK:		mov	r13, 4(r12)
 
 %S = type { i16, i16 }
 @baz = common global %S zeroinitializer, align 1
@@ -51,7 +51,7 @@ define void @am6(i16 %a) nounwind {
 	ret void
 }
 ; CHECK-LABEL: am6:
-; CHECK:		mov.w	r12, &baz+2
+; CHECK:		mov	r12, &baz+2
 
 %T = type { i16, [2 x i8] }
 @duh = external global %T
diff --git a/llvm/test/CodeGen/MSP430/Inst16mi.ll b/llvm/test/CodeGen/MSP430/Inst16mi.ll
index 38c16f2ba23..bb99e28a1ba 100644
--- a/llvm/test/CodeGen/MSP430/Inst16mi.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16mi.ll
@@ -6,14 +6,14 @@ target triple = "msp430-generic-generic"
 
 define void @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w	#2, &foo
+; CHECK: mov	#2, &foo
 	store i16 2, i16 * @foo
 	ret void
 }
 
 define void @add() nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w	#2, &foo
+; CHECK: incd	&foo
 	%1 = load i16, i16* @foo
 	%2 = add i16 %1, 2
 	store i16 %2, i16 * @foo
@@ -22,7 +22,7 @@ define void @add() nounwind {
 
 define void @and() nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	#2, &foo
+; CHECK: and	#2, &foo
 	%1 = load i16, i16* @foo
 	%2 = and i16 %1, 2
 	store i16 %2, i16 * @foo
@@ -31,7 +31,7 @@ define void @and() nounwind {
 
 define void @bis() nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	#2, &foo
+; CHECK: bis	#2, &foo
 	%1 = load i16, i16* @foo
 	%2 = or i16 %1, 2
 	store i16 %2, i16 * @foo
@@ -40,7 +40,7 @@ define void @bis() nounwind {
 
 define void @xor() nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	#2, &foo
+; CHECK: xor	#2, &foo
 	%1 = load i16, i16* @foo
 	%2 = xor i16 %1, 2
 	store i16 %2, i16 * @foo
diff --git a/llvm/test/CodeGen/MSP430/Inst16mm.ll b/llvm/test/CodeGen/MSP430/Inst16mm.ll
index 14a799b9171..21fab42fd59 100644
--- a/llvm/test/CodeGen/MSP430/Inst16mm.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16mm.ll
@@ -6,7 +6,7 @@ target triple = "msp430-generic-generic"
 
 define void @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w	&bar, &foo
+; CHECK: mov	&bar, &foo
         %1 = load i16, i16* @bar
         store i16 %1, i16* @foo
         ret void
@@ -14,7 +14,7 @@ define void @mov() nounwind {
 
 define void @add() nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w	&bar, &foo
+; CHECK: add	&bar, &foo
 	%1 = load i16, i16* @bar
 	%2 = load i16, i16* @foo
 	%3 = add i16 %2, %1
@@ -24,7 +24,7 @@ define void @add() nounwind {
 
 define void @and() nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	&bar, &foo
+; CHECK: and	&bar, &foo
 	%1 = load i16, i16* @bar
 	%2 = load i16, i16* @foo
 	%3 = and i16 %2, %1
@@ -34,7 +34,7 @@ define void @and() nounwind {
 
 define void @bis() nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	&bar, &foo
+; CHECK: bis	&bar, &foo
 	%1 = load i16, i16* @bar
 	%2 = load i16, i16* @foo
 	%3 = or i16 %2, %1
@@ -44,7 +44,7 @@ define void @bis() nounwind {
 
 define void @xor() nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	&bar, &foo
+; CHECK: xor	&bar, &foo
 	%1 = load i16, i16* @bar
 	%2 = load i16, i16* @foo
 	%3 = xor i16 %2, %1
@@ -64,6 +64,6 @@ entry:
  %0 = load i16, i16* %retval                          ; <i16> [#uses=1]
  ret i16 %0
 ; CHECK-LABEL: mov2:
-; CHECK-DAG:	mov.w	2(r1), 6(r1)
-; CHECK-DAG:	mov.w	0(r1), 4(r1)
+; CHECK-DAG:	mov	2(r1), 6(r1)
+; CHECK-DAG:	mov	0(r1), 4(r1)
 }
diff --git a/llvm/test/CodeGen/MSP430/Inst16mr.ll b/llvm/test/CodeGen/MSP430/Inst16mr.ll
index 847c093f408..e3f23d9c562 100644
--- a/llvm/test/CodeGen/MSP430/Inst16mr.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16mr.ll
@@ -5,14 +5,14 @@ target triple = "msp430-generic-generic"
 
 define void @mov(i16 %a) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w	r12, &foo
+; CHECK: mov	r12, &foo
 	store i16 %a, i16* @foo
 	ret void
 }
 
 define void @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w	r12, &foo
+; CHECK: add	r12, &foo
 	%1 = load i16, i16* @foo
 	%2 = add i16 %a, %1
 	store i16 %2, i16* @foo
@@ -21,7 +21,7 @@ define void @add(i16 %a) nounwind {
 
 define void @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	r12, &foo
+; CHECK: and	r12, &foo
 	%1 = load i16, i16* @foo
 	%2 = and i16 %a, %1
 	store i16 %2, i16* @foo
@@ -30,7 +30,7 @@ define void @and(i16 %a) nounwind {
 
 define void @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	r12, &foo
+; CHECK: bis	r12, &foo
 	%1 = load i16, i16* @foo
 	%2 = or i16 %a, %1
 	store i16 %2, i16* @foo
@@ -39,7 +39,7 @@ define void @bis(i16 %a) nounwind {
 
 define void @bic(i16 zeroext %m) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w   r12, &foo
+; CHECK: bic   r12, &foo
         %1 = xor i16 %m, -1
         %2 = load i16, i16* @foo
         %3 = and i16 %2, %1
@@ -49,7 +49,7 @@ define void @bic(i16 zeroext %m) nounwind {
 
 define void @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	r12, &foo
+; CHECK: xor	r12, &foo
 	%1 = load i16, i16* @foo
 	%2 = xor i16 %a, %1
 	store i16 %2, i16* @foo
diff --git a/llvm/test/CodeGen/MSP430/Inst16ri.ll b/llvm/test/CodeGen/MSP430/Inst16ri.ll
index 3a4bb6a93d9..58b2791194a 100644
--- a/llvm/test/CodeGen/MSP430/Inst16ri.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16ri.ll
@@ -4,34 +4,34 @@ target triple = "msp430-generic-generic"
 
 define i16 @mov() nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w	#1, r12
+; CHECK: mov	#1, r12
 	ret i16 1
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w	#1, r12
+; CHECK: inc	r12
 	%1 = add i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	#1, r12
+; CHECK: and	#1, r12
 	%1 = and i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	#1, r12
+; CHECK: bis	#1, r12
 	%1 = or i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	#1, r12
+; CHECK: xor	#1, r12
 	%1 = xor i16 %a, 1
 	ret i16 %1
 }
diff --git a/llvm/test/CodeGen/MSP430/Inst16rm.ll b/llvm/test/CodeGen/MSP430/Inst16rm.ll
index 44b8f39d8fa..8a3cd0a46fb 100644
--- a/llvm/test/CodeGen/MSP430/Inst16rm.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16rm.ll
@@ -5,7 +5,7 @@ target triple = "msp430-generic-generic"
 
 define i16 @add(i16 %a) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w	&foo, r12
+; CHECK: add	&foo, r12
 	%1 = load i16, i16* @foo
 	%2 = add i16 %a, %1
 	ret i16 %2
@@ -13,7 +13,7 @@ define i16 @add(i16 %a) nounwind {
 
 define i16 @and(i16 %a) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	&foo, r12
+; CHECK: and	&foo, r12
 	%1 = load i16, i16* @foo
 	%2 = and i16 %a, %1
 	ret i16 %2
@@ -21,7 +21,7 @@ define i16 @and(i16 %a) nounwind {
 
 define i16 @bis(i16 %a) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	&foo, r12
+; CHECK: bis	&foo, r12
 	%1 = load i16, i16* @foo
 	%2 = or i16 %a, %1
 	ret i16 %2
@@ -29,7 +29,7 @@ define i16 @bis(i16 %a) nounwind {
 
 define i16  @bic(i16 %a) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w	&foo, r12
+; CHECK: bic	&foo, r12
         %1 = load i16, i16* @foo
         %2 = xor i16 %1, -1
         %3 = and i16 %a, %2
@@ -38,7 +38,7 @@ define i16  @bic(i16 %a) nounwind {
 
 define i16 @xor(i16 %a) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	&foo, r12
+; CHECK: xor	&foo, r12
 	%1 = load i16, i16* @foo
 	%2 = xor i16 %a, %1
 	ret i16 %2
diff --git a/llvm/test/CodeGen/MSP430/Inst16rr.ll b/llvm/test/CodeGen/MSP430/Inst16rr.ll
index 75440ca2b40..124d42113a2 100644
--- a/llvm/test/CodeGen/MSP430/Inst16rr.ll
+++ b/llvm/test/CodeGen/MSP430/Inst16rr.ll
@@ -4,34 +4,34 @@ target triple = "msp430-generic-generic"
 
 define i16 @mov(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.w	r13, r12
+; CHECK: mov	r13, r12
 	ret i16 %b
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.w	r13, r12
+; CHECK: add	r13, r12
 	%1 = add i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	r13, r12
+; CHECK: and	r13, r12
 	%1 = and i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	r13, r12
+; CHECK: bis	r13, r12
 	%1 = or i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @bic(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: bic:
-; CHECK: bic.w	r13, r12
+; CHECK: bic	r13, r12
         %1 = xor i16 %b, -1
         %2 = and i16 %a, %1
         ret i16 %2
@@ -39,7 +39,7 @@ define i16 @bic(i16 %a, i16 %b) nounwind {
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	r13, r12
+; CHECK: xor	r13, r12
 	%1 = xor i16 %a, %b
 	ret i16 %1
 }
diff --git a/llvm/test/CodeGen/MSP430/Inst8mi.ll b/llvm/test/CodeGen/MSP430/Inst8mi.ll
index ff22d7e1eb3..36eb3f91f84 100644
--- a/llvm/test/CodeGen/MSP430/Inst8mi.ll
+++ b/llvm/test/CodeGen/MSP430/Inst8mi.ll
@@ -12,7 +12,7 @@ define void @mov() nounwind {
 
 define void @add() nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b	#2, &foo
+; CHECK: incd.b	&foo
 	%1 = load i8, i8* @foo
 	%2 = add i8 %1, 2
 	store i8 %2, i8 * @foo
diff --git a/llvm/test/CodeGen/MSP430/Inst8ri.ll b/llvm/test/CodeGen/MSP430/Inst8ri.ll
index 0e50f17f2a5..ff3dee8bfb9 100644
--- a/llvm/test/CodeGen/MSP430/Inst8ri.ll
+++ b/llvm/test/CodeGen/MSP430/Inst8ri.ll
@@ -10,7 +10,7 @@ define i8 @mov() nounwind {
 
 define i8 @add(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: add:
-; CHECK: add.b	#1, r12
+; CHECK: inc.b	r12
 	%1 = add i8 %a, 1
 	ret i8 %1
 }
diff --git a/llvm/test/CodeGen/MSP430/Inst8rr.ll b/llvm/test/CodeGen/MSP430/Inst8rr.ll
index f37bc32a28f..20c4fa5aacf 100644
--- a/llvm/test/CodeGen/MSP430/Inst8rr.ll
+++ b/llvm/test/CodeGen/MSP430/Inst8rr.ll
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
 
 define i8 @mov(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: mov:
-; CHECK: mov.{{[bw]}} r13, r12
+; CHECK: mov r13, r12
 	ret i8 %b
 }
 
@@ -17,14 +17,14 @@ define i8 @add(i8 %a, i8 %b) nounwind {
 
 define i8 @and(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: and:
-; CHECK: and.w	r13, r12
+; CHECK: and	r13, r12
 	%1 = and i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: bis:
-; CHECK: bis.w	r13, r12
+; CHECK: bis	r13, r12
 	%1 = or i8 %a, %b
 	ret i8 %1
 }
@@ -39,7 +39,7 @@ define i8 @bic(i8 %a, i8 %b) nounwind {
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
 ; CHECK-LABEL: xor:
-; CHECK: xor.w	r13, r12
+; CHECK: xor	r13, r12
 	%1 = xor i8 %a, %b
 	ret i8 %1
 }
diff --git a/llvm/test/CodeGen/MSP430/asm-clobbers.ll b/llvm/test/CodeGen/MSP430/asm-clobbers.ll
index 216a3fe4018..0a0335057f1 100644
--- a/llvm/test/CodeGen/MSP430/asm-clobbers.ll
+++ b/llvm/test/CodeGen/MSP430/asm-clobbers.ll
@@ -6,8 +6,8 @@ target triple = "msp430---elf"
 define void @test() {
 entry:
 ; CHECK-LABEL: test:
-; CHECK: push.w r10
+; CHECK: push r10
   call void asm sideeffect "", "~{r10}"()
-; CHECK: pop.w r10
+; CHECK: pop r10
   ret void
 }
diff --git a/llvm/test/CodeGen/MSP430/bit.ll b/llvm/test/CodeGen/MSP430/bit.ll
index 172822fbb5f..a4b781243b4 100644
--- a/llvm/test/CodeGen/MSP430/bit.ll
+++ b/llvm/test/CodeGen/MSP430/bit.ll
@@ -93,7 +93,7 @@ define i16 @bitwrr(i16 %a, i16 %b) nounwind {
 	ret i16 %t3
 }
 ; CHECK-LABEL: bitwrr:
-; CHECK: bit.w	r13, r12
+; CHECK: bit	r13, r12
 
 define i16 @bitwri(i16 %a) nounwind {
 	%t1 = and i16 %a, 4080
@@ -102,7 +102,7 @@ define i16 @bitwri(i16 %a) nounwind {
 	ret i16 %t3
 }
 ; CHECK-LABEL: bitwri:
-; CHECK: bit.w	#4080, r12
+; CHECK: bit	#4080, r12
 
 define i16 @bitwir(i16 %a) nounwind {
 	%t1 = and i16 4080, %a
@@ -111,7 +111,7 @@ define i16 @bitwir(i16 %a) nounwind {
 	ret i16 %t3
 }
 ; CHECK-LABEL: bitwir:
-; CHECK: bit.w	#4080, r12
+; CHECK: bit	#4080, r12
 
 define i16 @bitwmi() nounwind {
 	%t1 = load i16, i16* @foo16
@@ -121,7 +121,7 @@ define i16 @bitwmi() nounwind {
 	ret i16 %t4
 }
 ; CHECK-LABEL: bitwmi:
-; CHECK: bit.w	#4080, &foo16
+; CHECK: bit	#4080, &foo16
 
 define i16 @bitwim() nounwind {
 	%t1 = load i16, i16* @foo16
@@ -131,7 +131,7 @@ define i16 @bitwim() nounwind {
 	ret i16 %t4
 }
 ; CHECK-LABEL: bitwim:
-; CHECK: bit.w	#4080, &foo16
+; CHECK: bit	#4080, &foo16
 
 define i16 @bitwrm(i16 %a) nounwind {
 	%t1 = load i16, i16* @foo16
@@ -141,7 +141,7 @@ define i16 @bitwrm(i16 %a) nounwind {
 	ret i16 %t4
 }
 ; CHECK-LABEL: bitwrm:
-; CHECK: bit.w	&foo16, r12
+; CHECK: bit	&foo16, r12
 
 define i16 @bitwmr(i16 %a) nounwind {
 	%t1 = load i16, i16* @foo16
@@ -151,7 +151,7 @@ define i16 @bitwmr(i16 %a) nounwind {
 	ret i16 %t4
 }
 ; CHECK-LABEL: bitwmr:
-; CHECK: bit.w	r12, &foo16
+; CHECK: bit	r12, &foo16
 
 define i16 @bitwmm() nounwind {
 	%t1 = load i16, i16* @foo16
@@ -162,5 +162,5 @@ define i16 @bitwmm() nounwind {
 	ret i16 %t5
 }
 ; CHECK-LABEL: bitwmm:
-; CHECK: bit.w	&bar16, &foo16
+; CHECK: bit	&bar16, &foo16
 
diff --git a/llvm/test/CodeGen/MSP430/byval.ll b/llvm/test/CodeGen/MSP430/byval.ll
index 401896b43c2..838e883d4be 100644
--- a/llvm/test/CodeGen/MSP430/byval.ll
+++ b/llvm/test/CodeGen/MSP430/byval.ll
@@ -9,7 +9,7 @@ target triple = "msp430---elf"
 define i16 @callee(%struct.Foo* byval %f) nounwind {
 entry:
 ; CHECK-LABEL: callee:
-; CHECK: mov.w 2(r1), r12
+; CHECK: mov 2(r1), r12
   %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
   %1 = load i16, i16* %0, align 2
   ret i16 %1
@@ -18,9 +18,9 @@ entry:
 define void @caller() nounwind {
 entry:
 ; CHECK-LABEL: caller:
-; CHECK: mov.w &foo+4, 4(r1)
-; CHECK-NEXT: mov.w &foo+2, 2(r1)
-; CHECK-NEXT: mov.w &foo, 0(r1)
+; CHECK: mov &foo+4, 4(r1)
+; CHECK-NEXT: mov &foo+2, 2(r1)
+; CHECK-NEXT: mov &foo, 0(r1)
   %call = call i16 @callee(%struct.Foo* byval @foo)
   ret void
 }
diff --git a/llvm/test/CodeGen/MSP430/cc_args.ll b/llvm/test/CodeGen/MSP430/cc_args.ll
index 70ac901f7e4..eb7e470a9b6 100644
--- a/llvm/test/CodeGen/MSP430/cc_args.ll
+++ b/llvm/test/CodeGen/MSP430/cc_args.ll
@@ -7,50 +7,50 @@ define void @test() #0 {
 entry:
 ; CHECK: test:
 
-; CHECK: mov.w #1, r12
+; CHECK: mov #1, r12
 ; CHECK: call #f_i16
   call void @f_i16(i16 1)
 
-; CHECK: mov.w #772, r12
-; CHECK: mov.w #258, r13
+; CHECK: mov #772, r12
+; CHECK: mov #258, r13
 ; CHECK: call #f_i32
   call void @f_i32(i32 16909060)
 
-; CHECK: mov.w #1800, r12
-; CHECK: mov.w #1286, r13
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
+; CHECK: mov #1800, r12
+; CHECK: mov #1286, r13
+; CHECK: mov #772, r14
+; CHECK: mov #258, r15
 ; CHECK: call #f_i64
   call void @f_i64(i64 72623859790382856)
 
-; CHECK: mov.w #772, r12
-; CHECK: mov.w #258, r13
-; CHECK: mov.w #1800, r14
-; CHECK: mov.w #1286, r15
+; CHECK: mov #772, r12
+; CHECK: mov #258, r13
+; CHECK: mov #1800, r14
+; CHECK: mov #1286, r15
 ; CHECK: call #f_i32_i32
   call void @f_i32_i32(i32 16909060, i32 84281096)
 
-; CHECK: mov.w #1, r12
-; CHECK: mov.w #772, r13
-; CHECK: mov.w #258, r14
-; CHECK: mov.w #2, r15
+; CHECK: mov #1, r12
+; CHECK: mov #772, r13
+; CHECK: mov #258, r14
+; CHECK: mov #2, r15
 ; CHECK: call #f_i16_i32_i16
   call void @f_i16_i32_i16(i16 1, i32 16909060, i16 2)
 
-; CHECK: mov.w #1286, 0(r1)
-; CHECK: mov.w #1, r12
-; CHECK: mov.w #772, r13
-; CHECK: mov.w #258, r14
-; CHECK: mov.w #1800, r15
+; CHECK: mov #1286, 0(r1)
+; CHECK: mov #1, r12
+; CHECK: mov #772, r13
+; CHECK: mov #258, r14
+; CHECK: mov #1800, r15
 ; CHECK: call #f_i16_i32_i32
   call void @f_i16_i32_i32(i16 1, i32 16909060, i32 84281096)
 
-; CHECK: mov.w #258, 6(r1)
-; CHECK: mov.w #772, 4(r1)
-; CHECK: mov.w #1286, 2(r1)
-; CHECK: mov.w #1800, 0(r1)
-; CHECK: mov.w #1, r12
-; CHECK: mov.w #2, r13
+; CHECK: mov #258, 6(r1)
+; CHECK: mov #772, 4(r1)
+; CHECK: mov #1286, 2(r1)
+; CHECK: mov #1800, 0(r1)
+; CHECK: mov #1, r12
+; CHECK: mov #2, r13
 ; CHECK: call #f_i16_i64_i16
   call void @f_i16_i64_i16(i16 1, i64 72623859790382856, i16 2)
 
@@ -63,75 +63,75 @@ entry:
 
 define void @f_i16(i16 %a) #0 {
 ; CHECK: f_i16:
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
   ret void
 }
 
 define void @f_i32(i32 %a) #0 {
 ; CHECK: f_i32:
-; CHECK: mov.w r13, &g_i32+2
-; CHECK: mov.w r12, &g_i32
+; CHECK: mov r13, &g_i32+2
+; CHECK: mov r12, &g_i32
   store volatile i32 %a, i32* @g_i32, align 2
   ret void
 }
 
 define void @f_i64(i64 %a) #0 {
 ; CHECK: f_i64:
-; CHECK: mov.w r15, &g_i64+6
-; CHECK: mov.w r14, &g_i64+4
-; CHECK: mov.w r13, &g_i64+2
-; CHECK: mov.w r12, &g_i64
+; CHECK: mov r15, &g_i64+6
+; CHECK: mov r14, &g_i64+4
+; CHECK: mov r13, &g_i64+2
+; CHECK: mov r12, &g_i64
   store volatile i64 %a, i64* @g_i64, align 2
   ret void
 }
 
 define void @f_i32_i32(i32 %a, i32 %b) #0 {
 ; CHECK: f_i32_i32:
-; CHECK: mov.w r13, &g_i32+2
-; CHECK: mov.w r12, &g_i32
+; CHECK: mov r13, &g_i32+2
+; CHECK: mov r12, &g_i32
   store volatile i32 %a, i32* @g_i32, align 2
-; CHECK: mov.w r15, &g_i32+2
-; CHECK: mov.w r14, &g_i32
+; CHECK: mov r15, &g_i32+2
+; CHECK: mov r14, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
   ret void
 }
 
 define void @f_i16_i32_i32(i16 %a, i32 %b, i32 %c) #0 {
 ; CHECK: f_i16_i32_i32:
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: mov.w r14, &g_i32+2
-; CHECK: mov.w r13, &g_i32
+; CHECK: mov r14, &g_i32+2
+; CHECK: mov r13, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
-; CHECK: mov.w r15, &g_i32
-; CHECK: mov.w 4(r4), &g_i32+2
+; CHECK: mov r15, &g_i32
+; CHECK: mov 4(r4), &g_i32+2
   store volatile i32 %c, i32* @g_i32, align 2
   ret void
 }
 
 define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
 ; CHECK: f_i16_i32_i16:
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: mov.w r14, &g_i32+2
-; CHECK: mov.w r13, &g_i32
+; CHECK: mov r14, &g_i32+2
+; CHECK: mov r13, &g_i32
   store volatile i32 %b, i32* @g_i32, align 2
-; CHECK: mov.w r15, &g_i16
+; CHECK: mov r15, &g_i16
   store volatile i16 %c, i16* @g_i16, align 2
   ret void
 }
 
 define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
 ; CHECK: f_i16_i64_i16:
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2
-;CHECK: mov.w 10(r4), &g_i64+6
-;CHECK: mov.w 8(r4), &g_i64+4
-;CHECK: mov.w 6(r4), &g_i64+2
-;CHECK: mov.w 4(r4), &g_i64
+;CHECK: mov 10(r4), &g_i64+6
+;CHECK: mov 8(r4), &g_i64+4
+;CHECK: mov 6(r4), &g_i64+2
+;CHECK: mov 4(r4), &g_i64
   store volatile i64 %b, i64* @g_i64, align 2
-;CHECK: mov.w r13, &g_i16
+;CHECK: mov r13, &g_i16
   store volatile i16 %c, i16* @g_i16, align 2
   ret void
 }
diff --git a/llvm/test/CodeGen/MSP430/cc_ret.ll b/llvm/test/CodeGen/MSP430/cc_ret.ll
index 937db6dbf3b..b4bb0554208 100644
--- a/llvm/test/CodeGen/MSP430/cc_ret.ll
+++ b/llvm/test/CodeGen/MSP430/cc_ret.ll
@@ -8,21 +8,21 @@ entry:
 ; CHECK: test:
 
 ; CHECK: call #f_i16
-; CHECK: mov.w r12, &g_i16
+; CHECK: mov r12, &g_i16
   %0 = call i16 @f_i16()
   store volatile i16 %0, i16* @g_i16
 
 ; CHECK: call #f_i32
-; CHECK: mov.w r13, &g_i32+2
-; CHECK: mov.w r12, &g_i32
+; CHECK: mov r13, &g_i32+2
+; CHECK: mov r12, &g_i32
   %1 = call i32 @f_i32()
   store volatile i32 %1, i32* @g_i32
 
 ; CHECK: call #f_i64
-; CHECK: mov.w r15, &g_i64+6
-; CHECK: mov.w r14, &g_i64+4
-; CHECK: mov.w r13, &g_i64+2
-; CHECK: mov.w r12, &g_i64
+; CHECK: mov r15, &g_i64+6
+; CHECK: mov r14, &g_i64+4
+; CHECK: mov r13, &g_i64+2
+; CHECK: mov r12, &g_i64
   %2 = call i64 @f_i64()
   store volatile i64 %2, i64* @g_i64
 
@@ -35,25 +35,25 @@ entry:
 
 define i16 @f_i16() #0 {
 ; CHECK: f_i16:
-; CHECK: mov.w #1, r12
+; CHECK: mov #1, r12
 ; CHECK: ret
   ret i16 1
 }
 
 define i32 @f_i32() #0 {
 ; CHECK: f_i32:
-; CHECK: mov.w #772, r12
-; CHECK: mov.w #258, r13
+; CHECK: mov #772, r12
+; CHECK: mov #258, r13
 ; CHECK: ret
   ret i32 16909060
 }
 
 define i64 @f_i64() #0 {
 ; CHECK: f_i64:
-; CHECK: mov.w #1800, r12
-; CHECK: mov.w #1286, r13
-; CHECK: mov.w #772, r14
-; CHECK: mov.w #258, r15
+; CHECK: mov #1800, r12
+; CHECK: mov #1286, r13
+; CHECK: mov #772, r14
+; CHECK: mov #258, r15
 ; CHECK: ret
   ret i64 72623859790382856
 }
diff --git a/llvm/test/CodeGen/MSP430/fp.ll b/llvm/test/CodeGen/MSP430/fp.ll
index 2559e23ae1f..87c4055829c 100644
--- a/llvm/test/CodeGen/MSP430/fp.ll
+++ b/llvm/test/CodeGen/MSP430/fp.ll
@@ -6,13 +6,13 @@ target triple = "msp430---elf"
 define void @fp() nounwind {
 entry:
 ; CHECK-LABEL: fp:
-; CHECK: push.w r4
-; CHECK: mov.w r1, r4
-; CHECK: sub.w #2, r1
+; CHECK: push r4
+; CHECK: mov r1, r4
+; CHECK: sub #2, r1
   %i = alloca i16, align 2
-; CHECK: mov.w #0, -2(r4)
+; CHECK: clr -2(r4)
   store i16 0, i16* %i, align 2
-; CHECK: pop.w r4
+; CHECK: pop r4
   ret void
 }
 
diff --git a/llvm/test/CodeGen/MSP430/jumptable.ll b/llvm/test/CodeGen/MSP430/jumptable.ll
index 49f23166a0a..6121f7ebed6 100644
--- a/llvm/test/CodeGen/MSP430/jumptable.ll
+++ b/llvm/test/CodeGen/MSP430/jumptable.ll
@@ -7,15 +7,15 @@ target triple = "msp430---elf"
 define i16 @test(i16 %i) #0 {
 entry:
 ; CHECK-LABEL: test:
-; CHECK:      sub.w   #4, r1
-; CHECK-NEXT: mov.w   r12, 0(r1)
-; CHECK-NEXT: cmp.w   #4, r12
+; CHECK:      sub   #4, r1
+; CHECK-NEXT: mov   r12, 0(r1)
+; CHECK-NEXT: cmp   #4, r12
 ; CHECK-NEXT: jhs     .LBB0_3
   %retval = alloca i16, align 2
   %i.addr = alloca i16, align 2
   store i16 %i, i16* %i.addr, align 2
   %0 = load i16, i16* %i.addr, align 2
-; CHECK:      rla.w r12
+; CHECK:      add   r12, r12
 ; CHECK-NEXT: br .LJTI0_0(r12)
   switch i16 %0, label %sw.default [
     i16 0, label %sw.bb
diff --git a/llvm/test/CodeGen/MSP430/memset.ll b/llvm/test/CodeGen/MSP430/memset.ll
index 10b506c60d9..0f83b607820 100644
--- a/llvm/test/CodeGen/MSP430/memset.ll
+++ b/llvm/test/CodeGen/MSP430/memset.ll
@@ -9,9 +9,9 @@ define void @test() nounwind {
 entry:
 ; CHECK-LABEL: test:
   %0 = load i8*, i8** @buf, align 2
-; CHECK: mov.w &buf, r12
-; CHECK-NEXT: mov.w #5, r13
-; CHECK-NEXT: mov.w #128, r14
+; CHECK: mov &buf, r12
+; CHECK-NEXT: mov #5, r13
+; CHECK-NEXT: mov #128, r14
 ; CHECK-NEXT: call #memset
   call void @llvm.memset.p0i8.i16(i8* %0, i8 5, i16 128, i1 false)
   ret void
diff --git a/llvm/test/CodeGen/MSP430/misched-msp430.ll b/llvm/test/CodeGen/MSP430/misched-msp430.ll
index 3d18fa005a6..f44f10ccd3e 100644
--- a/llvm/test/CodeGen/MSP430/misched-msp430.ll
+++ b/llvm/test/CodeGen/MSP430/misched-msp430.ll
@@ -10,7 +10,7 @@ target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
 ; only verifies that the code generator ran successfully.
 ;
 ; CHECK-LABEL: @f
-; CHECK: mov.w &y, &x
+; CHECK: mov &y, &x
 ; CHECK: ret
 define void @f() {
 entry:
diff --git a/llvm/test/CodeGen/MSP430/postinc.ll b/llvm/test/CodeGen/MSP430/postinc.ll
index 75a927f33fc..20ee8fb3c85 100644
--- a/llvm/test/CodeGen/MSP430/postinc.ll
+++ b/llvm/test/CodeGen/MSP430/postinc.ll
@@ -12,7 +12,7 @@ for.body:                                         ; preds = %for.body, %entry
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: add:
-; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
+; CHECK: add @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = add i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
@@ -34,7 +34,7 @@ for.body:                                         ; preds = %for.body, %entry
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: sub:
-; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
+; CHECK: sub @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = sub i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
@@ -56,7 +56,7 @@ for.body:                                         ; preds = %for.body, %entry
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: or:
-; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
+; CHECK: bis @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = or i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
@@ -78,7 +78,7 @@ for.body:                                         ; preds = %for.body, %entry
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: xor:
-; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
+; CHECK: xor @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = xor i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
@@ -100,7 +100,7 @@ for.body:                                         ; preds = %for.body, %entry
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16, i16* %a, i16 %i.010   ; <i16*> [#uses=1]
 ; CHECK-LABEL: and:
-; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
+; CHECK: and @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16, i16* %arrayidx                     ; <i16> [#uses=1]
   %add = and i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
   %inc = add i16 %i.010, 1                        ; <i16> [#uses=2]
diff --git a/llvm/test/CodeGen/MSP430/select-use-sr.ll b/llvm/test/CodeGen/MSP430/select-use-sr.ll
index 3f67fb85f79..159fc93db5a 100644
--- a/llvm/test/CodeGen/MSP430/select-use-sr.ll
+++ b/llvm/test/CodeGen/MSP430/select-use-sr.ll
@@ -6,8 +6,8 @@ target triple = "msp430"
 ; Test that CMP instruction is not removed by MachineCSE.
 ;
 ; CHECK-LABEL: @f
-; CHECK: cmp.w r15, r13
-; CHECK: cmp.w r15, r13
+; CHECK: cmp r15, r13
+; CHECK: cmp r15, r13
 ; CHECK-NEXT: jeq .LBB0_2
 define i16 @f(i16, i16, i16, i16) {
 entry:
diff --git a/llvm/test/CodeGen/MSP430/setcc.ll b/llvm/test/CodeGen/MSP430/setcc.ll
index 6e2ec8ea3ea..52baf642903 100644
--- a/llvm/test/CodeGen/MSP430/setcc.ll
+++ b/llvm/test/CodeGen/MSP430/setcc.ll
@@ -9,10 +9,10 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind {
 	ret i16 %t3
 }
 ; CHECK-LABEL: sccweqand:
-; CHECK:	bit.w	r13, r12
-; CHECK:	mov.w	r2, r12
-; CHECK:	rra.w   r12
-; CHECK:	and.w	#1, r12
+; CHECK:	bit	r13, r12
+; CHECK:	mov	r2, r12
+; CHECK:	rra   r12
+; CHECK:	and	#1, r12
 
 define i16 @sccwneand(i16 %a, i16 %b) nounwind {
 	%t1 = and i16 %a, %b
@@ -21,9 +21,9 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind {
 	ret i16 %t3
 }
 ; CHECK-LABEL: sccwneand:
-; CHECK: 	bit.w	r13, r12
-; CHECK:	mov.w	r2, r12
-; CHECK:	and.w	#1, r12
+; CHECK: 	bit	r13, r12
+; CHECK:	mov	r2, r12
+; CHECK:	and	#1, r12
 
 define i16 @sccwne(i16 %a, i16 %b) nounwind {
 	%t1 = icmp ne i16 %a, %b
@@ -31,11 +31,11 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK-LABEL:sccwne:
-; CHECK:	cmp.w	r13, r12
-; CHECK:	mov.w	r2, r13
-; CHECK:	rra.w	r13
-; CHECK:	mov.w	#1, r12
-; CHECK:	bic.w	r13, r12
+; CHECK:	cmp	r13, r12
+; CHECK:	mov	r2, r13
+; CHECK:	rra	r13
+; CHECK:	mov	#1, r12
+; CHECK:	bic	r13, r12
 
 define i16 @sccweq(i16 %a, i16 %b) nounwind {
 	%t1 = icmp eq i16 %a, %b
@@ -43,10 +43,10 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK-LABEL:sccweq:
-; CHECK:	cmp.w	r13, r12
-; CHECK:	mov.w	r2, r12
-; CHECK:	rra.w	r12
-; CHECK:	and.w	#1, r12
+; CHECK:	cmp	r13, r12
+; CHECK:	mov	r2, r12
+; CHECK:	rra	r12
+; CHECK:	and	#1, r12
 
 define i16 @sccwugt(i16 %a, i16 %b) nounwind {
 	%t1 = icmp ugt i16 %a, %b
@@ -54,9 +54,9 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK-LABEL:sccwugt:
-; CHECK:	cmp.w	r12, r13
-; CHECK:	mov.w	#1, r12
-; CHECK:	bic.w	r2, r12
+; CHECK:	cmp	r12, r13
+; CHECK:	mov	#1, r12
+; CHECK:	bic	r2, r12
 
 define i16 @sccwuge(i16 %a, i16 %b) nounwind {
 	%t1 = icmp uge i16 %a, %b
@@ -64,9 +64,9 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK-LABEL:sccwuge:
-; CHECK:	cmp.w	r13, r12
-; CHECK:	mov.w	r2, r12
-; CHECK:	and.w	#1, r12
+; CHECK:	cmp	r13, r12
+; CHECK:	mov	r2, r12
+; CHECK:	and	#1, r12
 
 define i16 @sccwult(i16 %a, i16 %b) nounwind {
 	%t1 = icmp ult i16 %a, %b
@@ -74,9 +74,9 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK-LABEL:sccwult:
-; CHECK:	cmp.w	r13, r12
-; CHECK:	mov.w	#1, r12
-; CHECK:	bic.w	r2, r12
+; CHECK:	cmp	r13, r12
+; CHECK:	mov	#1, r12
+; CHECK:	bic	r2, r12
 
 define i16 @sccwule(i16 %a, i16 %b) nounwind {
 	%t1 = icmp ule i16 %a, %b
@@ -84,9 +84,9 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK-LABEL:sccwule:
-; CHECK:	cmp.w	r12, r13
-; CHECK:	mov.w	r2, r12
-; CHECK:	and.w	#1, r12
+; CHECK:	cmp	r12, r13
+; CHECK:	mov	r2, r12
+; CHECK:	and	#1, r12
 
 define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
 	%t1 = icmp sgt i16 %a, %b
diff --git a/llvm/test/CodeGen/MSP430/shifts.ll b/llvm/test/CodeGen/MSP430/shifts.ll
index 22ae59ef4b0..6d4050f42be 100644
--- a/llvm/test/CodeGen/MSP430/shifts.ll
+++ b/llvm/test/CodeGen/MSP430/shifts.ll
@@ -21,7 +21,7 @@ entry:
 define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
 entry:
 ; CHECK: shl8
-; CHECK: rla.b
+; CHECK: add.b
   %shl = shl i8 %a, %cnt
   ret i8 %shl
 }
@@ -29,7 +29,7 @@ entry:
 define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
 ; CHECK-LABEL: lshr16:
-; CHECK: rrc.w
+; CHECK: rrc
   %shr = lshr i16 %a, %cnt
   ret i16 %shr
 }
@@ -37,7 +37,7 @@ entry:
 define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
 ; CHECK-LABEL: ashr16:
-; CHECK: rra.w
+; CHECK: rra
   %shr = ashr i16 %a, %cnt
   ret i16 %shr
 }
@@ -45,7 +45,7 @@ entry:
 define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
 ; CHECK-LABEL: shl16:
-; CHECK: rla.w
+; CHECK: add
   %shl = shl i16 %a, %cnt
   ret i16 %shl
 }
diff --git a/llvm/test/CodeGen/MSP430/struct-return.ll b/llvm/test/CodeGen/MSP430/struct-return.ll
index c28bf06af43..a52ea1b702a 100644
--- a/llvm/test/CodeGen/MSP430/struct-return.ll
+++ b/llvm/test/CodeGen/MSP430/struct-return.ll
@@ -9,14 +9,14 @@ target triple = "msp430---elf"
 
 define %s @fred() #0 {
 ; CHECK-LABEL: fred:
-; CHECK: mov.w	#2314, 14(r12)
-; CHECK: mov.w	#2828, 12(r12)
-; CHECK: mov.w	#3342, 10(r12)
-; CHECK: mov.w	#3840, 8(r12)
-; CHECK: mov.w	#258, 6(r12)
-; CHECK: mov.w	#772, 4(r12)
-; CHECK: mov.w	#1286, 2(r12)
-; CHECK: mov.w	#1800, 0(r12)
+; CHECK: mov	#2314, 14(r12)
+; CHECK: mov	#2828, 12(r12)
+; CHECK: mov	#3342, 10(r12)
+; CHECK: mov	#3840, 8(r12)
+; CHECK: mov	#258, 6(r12)
+; CHECK: mov	#772, 4(r12)
+; CHECK: mov	#1286, 2(r12)
+; CHECK: mov	#1800, 0(r12)
   ret %s {i64 72623859790382856, i64 651345242494996224} 
 }
 
diff --git a/llvm/test/CodeGen/MSP430/struct_layout.ll b/llvm/test/CodeGen/MSP430/struct_layout.ll
index 60ae9f09b4e..4c5a131acca 100644
--- a/llvm/test/CodeGen/MSP430/struct_layout.ll
+++ b/llvm/test/CodeGen/MSP430/struct_layout.ll
@@ -5,7 +5,7 @@ target triple = "msp430"
 %struct.X = type { i8 }
 
 ; CHECK-LABEL: @foo
-; CHECK: sub.w   #4, r1
+; CHECK: sub   #4, r1
 ; CHECK: mov.b   #1, 3(r1)
 define void @foo() {
   %1 = alloca %struct.X
@@ -21,7 +21,7 @@ define void @foo() {
 }
 
 ; CHECK-LABEL: @bar
-; CHECK: sub.w   #4, r1
+; CHECK: sub   #4, r1
 ; CHECK: mov.b   #1, 3(r1)
 define void @bar() {
   %1 = alloca [3 x %struct.X]
@@ -40,8 +40,8 @@ define void @bar() {
 %struct.Y = type { i8, i16 }
 
 ; CHECK-LABEL: @baz
-; CHECK: sub.w   #8, r1
-; CHECK: mov.w   #2, 6(r1)
+; CHECK: sub   #8, r1
+; CHECK: mov   #2, 6(r1)
 define void @baz() {
   %1 = alloca %struct.Y, align 2
   %2 = alloca %struct.Y, align 2
diff --git a/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll b/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll
index cca83509cf4..a2ddf8a0b08 100644
--- a/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll
+++ b/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll
@@ -5,11 +5,11 @@ target triple = "msp430---elf"
 
 define void @test() #0 {
 ; CHECK-LABEL: test:
-; CHECK: sub.w #2, r1
+; CHECK: sub #2, r1
   %1 = alloca i8, align 1
-; CHECK-NEXT: mov.b #0, 1(r1)
+; CHECK-NEXT: clr.b 1(r1)
   store i8 0, i8* %1, align 1
-; CHECK-NEXT: add.w #2, r1
+; CHECK-NEXT: add #2, r1
 ; CHECK-NEXT: ret
   ret void
 }
diff --git a/llvm/test/CodeGen/MSP430/vararg.ll b/llvm/test/CodeGen/MSP430/vararg.ll
index 3501861f575..edb61d2221e 100644
--- a/llvm/test/CodeGen/MSP430/vararg.ll
+++ b/llvm/test/CodeGen/MSP430/vararg.ll
@@ -10,12 +10,12 @@ declare void @llvm.va_copy(i8*, i8*) nounwind
 define void @va_start(i16 %a, ...) nounwind {
 entry:
 ; CHECK-LABEL: va_start:
-; CHECK: sub.w #2, r1
+; CHECK: sub #2, r1
   %vl = alloca i8*, align 2
   %vl1 = bitcast i8** %vl to i8*
-; CHECK-NEXT: mov.w r1, [[REG:r[0-9]+]]
-; CHECK-NEXT: add.w #6, [[REG]]
-; CHECK-NEXT: mov.w [[REG]], 0(r1)
+; CHECK-NEXT: mov r1, [[REG:r[0-9]+]]
+; CHECK-NEXT: add #6, [[REG]]
+; CHECK-NEXT: mov [[REG]], 0(r1)
   call void @llvm.va_start(i8* %vl1)
   call void @llvm.va_end(i8* %vl1)
   ret void
@@ -26,11 +26,11 @@ entry:
 ; CHECK-LABEL: va_arg:
   %vl.addr = alloca i8*, align 2
   store i8* %vl, i8** %vl.addr, align 2
-; CHECK: mov.w r12, [[REG:r[0-9]+]]
-; CHECK-NEXT: add.w #2, [[REG]]
-; CHECK-NEXT: mov.w [[REG]], 0(r1)
+; CHECK: mov r12, [[REG:r[0-9]+]]
+; CHECK-NEXT: incd [[REG]]
+; CHECK-NEXT: mov [[REG]], 0(r1)
   %0 = va_arg i8** %vl.addr, i16
-; CHECK-NEXT: mov.w 0(r12), r12
+; CHECK-NEXT: mov 0(r12), r12
   ret i16 %0
 }
 
@@ -39,11 +39,11 @@ entry:
 ; CHECK-LABEL: va_copy:
   %vl.addr = alloca i8*, align 2
   %vl2 = alloca i8*, align 2
-; CHECK-DAG: mov.w r12, 2(r1)
+; CHECK-DAG: mov r12, 2(r1)
   store i8* %vl, i8** %vl.addr, align 2
   %0 = bitcast i8** %vl2 to i8*
   %1 = bitcast i8** %vl.addr to i8*
-; CHECK-DAG: mov.w r12, 0(r1)
+; CHECK-DAG: mov r12, 0(r1)
   call void @llvm.va_copy(i8* %0, i8* %1)
   ret void
 }