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| author | Job Noorman <jobnoorman@gmail.com> | 2014-04-02 13:13:56 +0000 |
|---|---|---|
| committer | Job Noorman <jobnoorman@gmail.com> | 2014-04-02 13:13:56 +0000 |
| commit | f7da105f3903dfb3a9153f542dbada8a9bb45a8a (patch) | |
| tree | 9771a1fde249bf2b24a47dfe27a05a9b646be078 /llvm/test/CodeGen/MSP430/fp.ll | |
| parent | f10662923aabd7066085c424f655209da78a15fc (diff) | |
| download | bcm5719-llvm-f7da105f3903dfb3a9153f542dbada8a9bb45a8a.tar.gz bcm5719-llvm-f7da105f3903dfb3a9153f542dbada8a9bb45a8a.zip | |
Mark FPB as a reserved register when needed.
llvm-svn: 205421
Diffstat (limited to 'llvm/test/CodeGen/MSP430/fp.ll')
| -rw-r--r-- | llvm/test/CodeGen/MSP430/fp.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MSP430/fp.ll b/llvm/test/CodeGen/MSP430/fp.ll index 018090566f1..b6ba22e47cc 100644 --- a/llvm/test/CodeGen/MSP430/fp.ll +++ b/llvm/test/CodeGen/MSP430/fp.ll @@ -15,3 +15,15 @@ entry: ; CHECK: pop.w r4 ret void } + +; Due to FPB not being marked as reserved, the register allocator used to select +; r4 as the register for the "r" constraint below. This test verifies that this +; does not happen anymore. Note that the only reason an ISR is used here is that +; the register allocator selects r4 first instead of fifth in a normal function. +define msp430_intrcc void @fpb_alloced() #0 { +; CHECK_LABEL: fpb_alloced: +; CHECK-NOT: mov.b #0, r4 +; CHECK: nop + call void asm sideeffect "nop", "r"(i8 0) + ret void +} |
