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| author | Michael Liao <michael.hliao@gmail.com> | 2019-07-03 02:00:21 +0000 |
|---|---|---|
| committer | Michael Liao <michael.hliao@gmail.com> | 2019-07-03 02:00:21 +0000 |
| commit | 80177ca5a9b0731b62943e30c7d8f39e7664bb82 (patch) | |
| tree | 6a25550f313815ad117b0209b7e21728dc85e1dc /llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll | |
| parent | cac1151845e6b55d38ecac014438e64f8feae687 (diff) | |
| download | bcm5719-llvm-80177ca5a9b0731b62943e30c7d8f39e7664bb82.tar.gz bcm5719-llvm-80177ca5a9b0731b62943e30c7d8f39e7664bb82.zip | |
[AMDGPU] Enable serializing of argument info.
Summary:
- Support serialization of all arguments in machine function info. This
enables fabricating MIR tests depending on argument info.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64096
llvm-svn: 364995
Diffstat (limited to 'llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index 4e233495f5f..9fbf484b2c0 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -19,6 +19,12 @@ ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' ; CHECK-NEXT: frameOffsetReg: '$sgpr101' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } +; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } +; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } ; CHECK-NEXT: body: define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 @@ -39,6 +45,9 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' ; CHECK-NEXT: frameOffsetReg: '$sgpr101' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' } +; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } ; CHECK-NEXT: body: define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { ret void @@ -57,6 +66,9 @@ define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' ; CHECK-NEXT: frameOffsetReg: '$sgpr5' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' } ; CHECK-NEXT: body: define void @function() { ret void @@ -75,6 +87,9 @@ define void @function() { ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' ; CHECK-NEXT: frameOffsetReg: '$sgpr5' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' } ; CHECK-NEXT: body: define void @function_nsz() #0 { ret void |
