MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.

This is an example of a function's body that uses the old syntax:

    body:
      - id: 0
        name: entry
        instructions:
          - '%eax = MOV32r0 implicit-def %eflags'
          - 'RETQ %eax'
    ...

The same body is now written like this:

    body: |
      bb.0.entry:
        %eax = MOV32r0 implicit-def %eflags
        RETQ %eax
    ...

This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:

   BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
      t2IT 1, 24, implicit-def %itstate
      %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
   }

This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.

llvm-svn: 244982

1 files changed, 23 insertions, 24 deletions

diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
index aeea9b2e3a5..e20cf376414 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
@@ -38,28 +38,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: [[@LINE+1]]:50: use of undefined target index 'constdata-start'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...