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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 13:13:18 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 13:13:18 +0000 |
| commit | d4e0a4fd2c74a41a32a9817667bb1394cc84f124 (patch) | |
| tree | d7dd14b3a7cb2b372325853d9408dbd9a5880cf2 /llvm/test/CodeGen/Inputs | |
| parent | 81f59a09f22fde3aaeffb97574ea438e511d5988 (diff) | |
| download | bcm5719-llvm-d4e0a4fd2c74a41a32a9817667bb1394cc84f124.tar.gz bcm5719-llvm-d4e0a4fd2c74a41a32a9817667bb1394cc84f124.zip | |
[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5
Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions
when targeting ARMv8, but they are actually present on any target with
FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an
M-profile core, but they have the same instructions so we model them
both as FPARMv8 in the ARM backend.
llvm-svn: 218763
Diffstat (limited to 'llvm/test/CodeGen/Inputs')
0 files changed, 0 insertions, 0 deletions
