[Hexagon][x86] add tests for bit-test; NFC

More coverage for D66687
(assuming we make this a generic combine with TLI hook).

llvm-svn: 369874

1 files changed, 98 insertions, 1 deletions

diff --git a/llvm/test/CodeGen/Hexagon/tstbit.ll b/llvm/test/CodeGen/Hexagon/tstbit.ll
index ac1799007f6..4f5ad329618 100644
--- a/llvm/test/CodeGen/Hexagon/tstbit.ll
+++ b/llvm/test/CodeGen/Hexagon/tstbit.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
 
 ; Function Attrs: nounwind readnone
 define i32 @f0(i32 %a0, i32 %a1) #0 {
@@ -20,4 +20,101 @@ b0:
   ret i32 %v3
 }
 
+define i64 @is_upper_bit_clear_i64(i64 %x) {
+; CHECK-LABEL: is_upper_bit_clear_i64:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = extractu(r1:0,#1,#37)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = togglebit(r0,#0)
+; CHECK-NEXT:     r1 = #0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %sh = lshr i64 %x, 37
+  %m = and i64 %sh, 1
+  %r = xor i64 %m, 1
+  ret i64 %r
+}
+
+define i64 @is_lower_bit_clear_i64(i64 %x) {
+; CHECK-LABEL: is_lower_bit_clear_i64:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = extractu(r1:0,#1,#27)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = togglebit(r0,#0)
+; CHECK-NEXT:     r1 = #0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %sh = lshr i64 %x, 27
+  %m = and i64 %sh, 1
+  %r = xor i64 %m, 1
+  ret i64 %r
+}
+
+define i32 @is_bit_clear_i32(i32 %x) {
+; CHECK-LABEL: is_bit_clear_i32:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 ^= lsr(r0,#27)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = and(r1,#1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %sh = lshr i32 %x, 27
+  %n = xor i32 %sh, -1
+  %r = and i32 %n, 1
+  ret i32 %r
+}
+
+define i16 @is_bit_clear_i16(i16 %x) {
+; CHECK-LABEL: is_bit_clear_i16:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 ^= lsr(r0,#7)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = and(r1,#1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %sh = lshr i16 %x, 7
+  %m = and i16 %sh, 1
+  %r = xor i16 %m, 1
+  ret i16 %r
+}
+
+define i8 @is_bit_clear_i8(i8 %x) {
+; CHECK-LABEL: is_bit_clear_i8:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 ^= lsr(r0,#3)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = and(r1,#1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %sh = lshr i8 %x, 3
+  %m = and i8 %sh, 1
+  %r = xor i8 %m, 1
+  ret i8 %r
+}
+
+
 attributes #0 = { nounwind readnone }