diff options
| author | Guozhi Wei <carrot@google.com> | 2019-08-08 20:25:23 +0000 |
|---|---|---|
| committer | Guozhi Wei <carrot@google.com> | 2019-08-08 20:25:23 +0000 |
| commit | 80347c3acc08a653cb4dd64411d86c35ac73011e (patch) | |
| tree | f44c9a35f5409f87d6e74ed03f5ffca7ff1bf9f5 /llvm/test/CodeGen/Hexagon | |
| parent | 8b49e0fd39f946d0d2e6e3979a893b89dec1d9e0 (diff) | |
| download | bcm5719-llvm-80347c3acc08a653cb4dd64411d86c35ac73011e.tar.gz bcm5719-llvm-80347c3acc08a653cb4dd64411d86c35ac73011e.zip | |
[MBP] Disable aggressive loop rotate in plain mode
Patch https://reviews.llvm.org/D43256 introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.
To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.
Differential Revision: https://reviews.llvm.org/D65673
llvm-svn: 368339
Diffstat (limited to 'llvm/test/CodeGen/Hexagon')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/bug6757-endloop.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/prof-early-if.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/redundant-branching2.ll | 2 |
4 files changed, 4 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll b/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll index 9fec47e54cd..a4e593fa2ba 100644 --- a/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll +++ b/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll @@ -4,10 +4,10 @@ ; This situation can arise due to tail duplication. ; CHECK: loop1([[LP:.LBB0_[0-9]+]] -; CHECK: endloop1 ; CHECK: [[LP]]: ; CHECK-NOT: loop1( ; CHECK: endloop1 +; CHECK: endloop1 %s.0 = type { i32, i8* } %s.1 = type { i32, i32, i32, i32 } diff --git a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll index 01983cfb969..ab8b00d6c90 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll @@ -2,11 +2,9 @@ ; Make sure that the loop in the end has only one basic block. ; CHECK-LABEL: fred -; CHECK: %b2 ; Rely on the comments, make sure the one for the loop header is present. ; CHECK: %loop -; CHECK: %should_merge -; CHECK: %exit +; CHECK-NOT: %should_merge target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/prof-early-if.ll b/llvm/test/CodeGen/Hexagon/prof-early-if.ll index b0f21110b7d..a5215a9b351 100644 --- a/llvm/test/CodeGen/Hexagon/prof-early-if.ll +++ b/llvm/test/CodeGen/Hexagon/prof-early-if.ll @@ -1,8 +1,8 @@ ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s ; Rely on the comments generated by llc. Check that "if.then" was not predicated. -; CHECK: b5 ; CHECK: b2 ; CHECK-NOT: if{{.*}}memd +; CHECK: b5 %s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] } %s.1 = type { i32, i32 } diff --git a/llvm/test/CodeGen/Hexagon/redundant-branching2.ll b/llvm/test/CodeGen/Hexagon/redundant-branching2.ll index e9305e9fd27..50007007d17 100644 --- a/llvm/test/CodeGen/Hexagon/redundant-branching2.ll +++ b/llvm/test/CodeGen/Hexagon/redundant-branching2.ll @@ -3,9 +3,9 @@ ; CHECK: memub ; CHECK: memub -; CHECK: cmp.eq ; CHECK: memub ; CHECK-NOT: if{{.*}}jump .LBB +; CHECK: cmp.eq target triple = "hexagon-unknown--elf" |
